復(fù)雜多核系統(tǒng)的調(diào)試系統(tǒng)設(shè)計與研究
發(fā)布時間：2018-09-08 10:53
【摘要】：隨著嵌入式系統(tǒng)與FPGA開發(fā)平臺的深度融合,使得基于FPGA的片上可編程系統(tǒng)(System-on-a-Programmable-Chip,SOPC)技術(shù)得到了前所未有的蓬勃發(fā)展。以專用FPGA芯片為核心的開發(fā)平臺,具有軟硬件“量體裁衣”的靈活選擇性和可編程特性,甚至可根據(jù)用戶設(shè)計需求進行個性化定制,因此受到行業(yè)開發(fā)者們青睞。基于FPGA內(nèi)嵌的可配置軟核,以及可復(fù)用的知識產(chǎn)權(quán)(IntellectualProperty, IP),通過總線與外圍硬件設(shè)備可實現(xiàn)微處理器技術(shù)、SOPC設(shè)計和軟硬協(xié)同設(shè)計等,大大降低設(shè)計難度和縮短系統(tǒng)開發(fā)時間,提高資源復(fù)用率。然而,隨著復(fù)雜多核SoC的設(shè)計復(fù)雜性的增加與性能的提升,使得軟硬件調(diào)試任務(wù)越來越艱巨,傳統(tǒng)的測試方法與調(diào)試手段無法在有限條件下保證芯片功能設(shè)計的正確性,而且在驗證上花費的代價越來越高,要想一次性成功完成芯片設(shè)計顯得越來越困難。因此,能夠提高調(diào)試質(zhì)量的多核調(diào)試技術(shù)是減少軟硬件調(diào)試時間和降低設(shè)計成本的關(guān)鍵,SOPC技術(shù)的出現(xiàn)可以極大改變傳統(tǒng)的調(diào)試方法,提高復(fù)雜多核SoC的調(diào)試效率。本文主要對基于NoC的復(fù)雜多核系統(tǒng)的調(diào)試技術(shù)進行了深入研究,基于SOPC技術(shù)思想設(shè)計并實現(xiàn)了一款實用的調(diào)試系統(tǒng),論文主要工作與研究內(nèi)容如下:首先,對當(dāng)前調(diào)試技術(shù)和項目組設(shè)計的復(fù)雜多核系統(tǒng)進行了研究與分析,完成了目標(biāo)系統(tǒng)的軟件指令自刷新功能,在此基礎(chǔ)上基于SOPC技術(shù)實現(xiàn)了一款具有可配置、可編程、可裁剪和可移植的調(diào)試系統(tǒng)架構(gòu),該架構(gòu)能夠完成對目標(biāo)系統(tǒng)的關(guān)鍵數(shù)據(jù)信息追蹤以及監(jiān)測、任務(wù)調(diào)度和系統(tǒng)控制等,可以還原系統(tǒng)的工作流程,具有很好的實用價值,大大降低復(fù)雜多核SoC調(diào)試的時間,加快芯片設(shè)計進程。其次,對調(diào)試系統(tǒng)架構(gòu)的各個關(guān)鍵模塊設(shè)計進行了深入研究與分析,主要包括根據(jù)目標(biāo)系統(tǒng)工作機制特點設(shè)計的調(diào)試結(jié)構(gòu)、調(diào)試系統(tǒng)命令和數(shù)據(jù)的傳輸機制、調(diào)試系統(tǒng)的四種調(diào)試模式、調(diào)試系統(tǒng)的調(diào)試接口(DebugInterface,DI)模塊以及相關(guān)的軟硬件模塊等,結(jié)合SOPC技術(shù)和軟硬協(xié)同設(shè)計方法實現(xiàn)了具有一定的高效性、實用性以及可移植特性的調(diào)試系統(tǒng),完成了針對目標(biāo)系統(tǒng)的調(diào)試控制指令設(shè)計和相應(yīng)的調(diào)試流程。最后,將本文設(shè)計與實現(xiàn)的調(diào)試系統(tǒng)集成到目標(biāo)系統(tǒng)中,基于Virtex-6 XC6VLX760 FPGA開發(fā)板進行調(diào)試系統(tǒng)的輸入輸出器件的協(xié)作測試,在目標(biāo)系統(tǒng)的測試任務(wù)集中,選取了經(jīng)典的大點FFT卷積運算進行算法分析與映射,在目標(biāo)系統(tǒng)中完成任務(wù)加載并進行調(diào)試系統(tǒng)的FPGA測試驗證。實驗結(jié)果表明,在不影響目標(biāo)系統(tǒng)正常任務(wù)執(zhí)行的情況下,通過友好的調(diào)試界面可以很好的完成關(guān)鍵數(shù)據(jù)信息監(jiān)測、任務(wù)追蹤和系統(tǒng)控制等調(diào)試需求,證明了本課題設(shè)計與實現(xiàn)的復(fù)雜多核系統(tǒng)的調(diào)試系統(tǒng)方案的可行性,該調(diào)試系統(tǒng)設(shè)計過程具有兩大特色,即SOPC技術(shù)思想和軟硬協(xié)同設(shè)計方法,并且滿足復(fù)雜多核SoC的調(diào)試需求,具有一定的實際應(yīng)用價值。
[Abstract]:With the deep integration of embedded system and FPGA development platform, the technology of system-on-a-Programmable-Chip (SOPC) based on FPGA has been flourishing unprecedentedly. Based on the configurable soft core embedded in the FPGA and the reusable intellectual property (IP), microprocessor technology, SOPC design and hardware-software co-design can be realized by bus and peripheral hardware devices, which greatly reduces the design difficulty and complexity. However, with the increase of complexity and performance of complex multi-core SoC design, the task of debugging software and hardware becomes more and more difficult. Traditional testing methods and debugging methods can not guarantee the correctness of chip function design under limited conditions, and the cost of verification increases. Therefore, the multi-core debugging technology which can improve the debugging quality is the key to reduce the debugging time and design cost. The appearance of SOPC technology can greatly change the traditional debugging methods and improve the debugging efficiency of complex multi-core SoC. The debugging technology of complex multi-core system based on NoC is deeply studied. A practical debugging system is designed and implemented based on SOPC technology. The main work and research contents of this paper are as follows: Firstly, the current debugging technology and the complex multi-core system designed by the project team are studied and analyzed, and the software finger of the target system is completed. Based on the SOPC technology, a debugging system architecture with configurable, programmable, tailorable and portable functions is implemented. The architecture can track and monitor the key data of the target system, schedule tasks and control the system, and restore the work flow of the system. It has a good practical price. Secondly, the design of the key modules of the debugging system architecture is deeply studied and analyzed, including the debugging structure designed according to the characteristics of the working mechanism of the target system, the transmission mechanism of the commands and data of the debugging system, and the four debugging mechanisms of the debugging system. The debugging system with high efficiency, practicability and portability is realized by combining SOPC technology with software and hardware co-design method. The debugging control instruction design and corresponding debugging process for the target system are completed. Then, the debugging system designed and implemented in this paper is integrated into the target system, and the input and output devices of the debugging system are tested cooperatively based on the Virtex-6XC6VLX760 FPGA development board. In the test task set of the target system, the classic large-point FFT convolution operation is selected for algorithm analysis and mapping, and the task addition is completed in the target system. The experimental results show that the debugging requirements such as key data information monitoring, task tracking and system control can be well fulfilled through a friendly debugging interface without affecting the normal task execution of the target system. The feasibility of the system scheme, the debugging system design process has two characteristics, namely, SOPC technology and hardware-software co-design method, and meets the debugging requirements of complex multi-core SoC, which has a certain practical value.
【學(xué)位授予單位】：合肥工業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TN47
本文編號：2230307
[Abstract]:With the deep integration of embedded system and FPGA development platform, the technology of system-on-a-Programmable-Chip (SOPC) based on FPGA has been flourishing unprecedentedly. Based on the configurable soft core embedded in the FPGA and the reusable intellectual property (IP), microprocessor technology, SOPC design and hardware-software co-design can be realized by bus and peripheral hardware devices, which greatly reduces the design difficulty and complexity. However, with the increase of complexity and performance of complex multi-core SoC design, the task of debugging software and hardware becomes more and more difficult. Traditional testing methods and debugging methods can not guarantee the correctness of chip function design under limited conditions, and the cost of verification increases. Therefore, the multi-core debugging technology which can improve the debugging quality is the key to reduce the debugging time and design cost. The appearance of SOPC technology can greatly change the traditional debugging methods and improve the debugging efficiency of complex multi-core SoC. The debugging technology of complex multi-core system based on NoC is deeply studied. A practical debugging system is designed and implemented based on SOPC technology. The main work and research contents of this paper are as follows: Firstly, the current debugging technology and the complex multi-core system designed by the project team are studied and analyzed, and the software finger of the target system is completed. Based on the SOPC technology, a debugging system architecture with configurable, programmable, tailorable and portable functions is implemented. The architecture can track and monitor the key data of the target system, schedule tasks and control the system, and restore the work flow of the system. It has a good practical price. Secondly, the design of the key modules of the debugging system architecture is deeply studied and analyzed, including the debugging structure designed according to the characteristics of the working mechanism of the target system, the transmission mechanism of the commands and data of the debugging system, and the four debugging mechanisms of the debugging system. The debugging system with high efficiency, practicability and portability is realized by combining SOPC technology with software and hardware co-design method. The debugging control instruction design and corresponding debugging process for the target system are completed. Then, the debugging system designed and implemented in this paper is integrated into the target system, and the input and output devices of the debugging system are tested cooperatively based on the Virtex-6XC6VLX760 FPGA development board. In the test task set of the target system, the classic large-point FFT convolution operation is selected for algorithm analysis and mapping, and the task addition is completed in the target system. The experimental results show that the debugging requirements such as key data information monitoring, task tracking and system control can be well fulfilled through a friendly debugging interface without affecting the normal task execution of the target system. The feasibility of the system scheme, the debugging system design process has two characteristics, namely, SOPC technology and hardware-software co-design method, and meets the debugging requirements of complex multi-core SoC, which has a certain practical value.
【學(xué)位授予單位】：合肥工業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2017
【分類號】：TN47
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