本文關(guān)鍵詞：基于FPGA的串行總線的研究與實現(xiàn)　出處：《南京航空航天大學(xué)》2013年碩士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： FPGA 串行總線 高速通信 PCI總線

【摘要】：智能在線高速煙草異物剔除系統(tǒng)是用于剔除煙草中異物的專用自動化設(shè)備。本課題研究的基于FPGA的串行總線是設(shè)備控制部分的主體。 傳統(tǒng)的剔除閥控制采用并行的方式，一個剔除閥對應(yīng)I/O板卡的一個I/O接口。該控制方式的傳輸方式是并行傳輸方案，信號容易受干擾，系統(tǒng)的安全性和可靠性低，并且連接需要使用大量傳輸電纜，工程造價高，檢修維護(hù)不便。為解決傳統(tǒng)剔除閥控制系統(tǒng)的不足，本課題設(shè)計了基于FPGA的串行總線，以替代原來的并行控制模塊。該串行總線的核心是基于FPGA設(shè)計的信號發(fā)送卡與信號接收卡。該設(shè)計目的是將工控機(jī)發(fā)出的并行信號高速轉(zhuǎn)換成串行信號傳輸，采用基于PCI總線的方式將計算機(jī)控制信號傳輸至基于FPGA設(shè)計的信號發(fā)送卡，該發(fā)送卡將并行信號轉(zhuǎn)換成串行信號傳遞給信號接收卡，，基于FPGA設(shè)計的接收卡將信號還原為并行信號并驅(qū)動剔除閥工作。該串行總線能解決現(xiàn)有的剔除閥與工控機(jī)之間信號易受干擾，接線繁雜，設(shè)備結(jié)構(gòu)繁復(fù)，后期維護(hù)困難等問題。 本文在進(jìn)行大量的理論研究和工程實踐的基礎(chǔ)上，闡述了串行通信的基本理論和高速數(shù)字系統(tǒng)設(shè)計的基本理論，研究了FPGA技術(shù)、Verilog HDL硬件描述語言的編寫方法及PCB技術(shù)，設(shè)計了PCI局部總線接口電路、電平轉(zhuǎn)換電路、端口地址設(shè)定與串行速率調(diào)節(jié)電路、數(shù)據(jù)串行輸出電路、數(shù)據(jù)接收電路、剔除閥驅(qū)動電路和信號發(fā)送卡與接收卡的PCB圖，并用Verilog HDL為設(shè)計的硬件電路編寫程序，實現(xiàn)相應(yīng)的時序功能和邏輯功能。 本課題研究的基于FPGA設(shè)計的串行總線已經(jīng)完成設(shè)計并制成樣品，通過實驗測試和現(xiàn)場試用證明了其可行性。
[Abstract]:Intelligent online high-speed tobacco foreign body culling system is a special automatic device used to eliminate foreign body in tobacco. The serial bus based on FPGA is the main part of the device control in this paper. The traditional culling valve control adopts parallel mode, and a culling valve corresponds to an I / O interface of the I / O card. The transmission mode of this control mode is parallel transmission scheme, and the signal is easily disturbed. The security and reliability of the system are low, and the connection needs a large number of transmission cables, the project cost is high, maintenance is inconvenient. This paper designs a serial bus based on FPGA. The core of the serial bus is a signal sending card and a signal receiving card designed based on FPGA. The purpose of this design is to convert the parallel signal from industrial control computer to serial signal transmission at high speed. Lose. The computer control signal is transmitted to the signal sending card based on FPGA by PCI bus. The card converts the parallel signal into serial signal and transfers it to the signal receiving card. The receiving card designed based on FPGA can restore the signal to parallel signal and drive the culling valve to work. The serial bus can solve the interference between the existing culling valve and the industrial computer, the connection is complicated, and the equipment structure is complicated. Late maintenance difficulties and other problems. On the basis of a lot of theoretical research and engineering practice, this paper expounds the basic theory of serial communication and the basic theory of high-speed digital system design, and studies the FPGA technology. The writing method of Verilog HDL hardware description language and PCB technology, the interface circuit of PCI local bus, the level conversion circuit, the port address setting and the serial rate adjusting circuit are designed. Data serial output circuit, data receiving circuit, eliminating valve drive circuit and the PCB diagram of signal sending card and receiving card are eliminated, and the program is written with Verilog HDL for the hardware circuit designed. The corresponding timing function and logic function are realized. The serial bus based on FPGA has been designed and made into a sample, which is proved to be feasible by experiments and field trials.
【學(xué)位授予單位】：南京航空航天大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：TP336

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本文編號：1421458