發(fā)布時(shí)間：2018-01-10 15:09

  本文關(guān)鍵詞：基于增益單元的抗輻射嵌入式存儲(chǔ)器研究　出處：《華中科技大學(xué)》2016年博士論文　論文類(lèi)型：學(xué)位論文

  更多相關(guān)文章： 抗輻射 嵌入式存儲(chǔ)器 增益單元 自適應(yīng)刷新 刷新周期 刷新功耗 隱式刷新

【摘要】：在空間環(huán)境中,高能粒子入射到半導(dǎo)體材料中產(chǎn)生大量電子-空穴對(duì),引發(fā)總劑量效應(yīng)和單粒子效應(yīng),使電子系統(tǒng)時(shí)刻面臨輻射效應(yīng)的威脅。單粒子效應(yīng)使電子系統(tǒng)中的數(shù)據(jù)發(fā)生錯(cuò)誤,導(dǎo)致控制系統(tǒng)和整個(gè)航天器發(fā)生故障。在航天器的電子系統(tǒng)中,占據(jù)芯片大部分面積的嵌入式存儲(chǔ)器受單粒子效應(yīng)的影響最為嚴(yán)重,是最脆弱的器件。當(dāng)前基于6T SRAM單元的嵌入式存儲(chǔ)器的抗輻射加固普遍會(huì)導(dǎo)致存儲(chǔ)器面積的大幅增加,最終使得電子系統(tǒng)的面積和成本大幅增加。另一方面,由于6T SRAM單元讀寫(xiě)操作的比率特性,其數(shù)據(jù)穩(wěn)定性隨工藝的發(fā)展而迅速下降。傳統(tǒng)的基于6T SRAM單元的抗輻射嵌入式存儲(chǔ)器存在明顯的不足。本文基于增益單元結(jié)構(gòu),對(duì)抗輻射嵌入式存儲(chǔ)器進(jìn)行了深入研究,取得的主要成果如下。首先,提出一種基于增益單元的抗總劑量效應(yīng)(Total Ionizing Dose:TID)和單粒子閂鎖(Single Evnet Latchup:SEL)加固的4P eDRAM單元。通過(guò)對(duì)增益單元的特性分析以及TID效應(yīng)和SEL效應(yīng)的原理的分析,提出一種新的抗TID/SEL加固的嵌入式存儲(chǔ)單元。對(duì)4P eDRAM單元進(jìn)行了詳細(xì)的分析,采用高閾值(H-VT)寫(xiě)訪問(wèn)管技術(shù)、負(fù)字線電壓技術(shù)(Negative Word Line:NWL),差分結(jié)構(gòu)和電壓上拉技術(shù)(Voltage Boosting technology:VBT)來(lái)改進(jìn)存儲(chǔ)單元的讀寫(xiě)性能和數(shù)據(jù)保持時(shí)間。該存儲(chǔ)單元與邏輯兼容,可以采用標(biāo)準(zhǔn)CMOS工藝,具有較好的存儲(chǔ)性能和較小的存儲(chǔ)單元面積。其次,提出雙模冗余(Dual-Modular Redundant:DMR)和列向比特間隔(Column Direction Bit-Interleaving:CDBI)相結(jié)合的抗單粒子翻轉(zhuǎn)(Single Event Upset:SEU)和多位翻轉(zhuǎn)(Multiple Cell Upset:MCU)的加固技術(shù)。通過(guò)對(duì)4P eDRAM單元的SEU特性和MCU特性的研究,提出采用DMR技術(shù)對(duì)4P eDRAM單元實(shí)現(xiàn)抗DMR加固。研究了DMR加固后的HGC eDRAM單元的MCU特性,提出CDBI技術(shù)使HGC eDRAM單元中的二個(gè)子單元在物理上隔離,實(shí)現(xiàn)抗MCU加固。仿真結(jié)果證實(shí),HGC eDRAM單元能夠在線性能量傳輸值(Linear Energy Transfor:LET)為120 MeV·cm2/mg的單粒子效應(yīng)下,依然能夠讀出正確的數(shù)據(jù),實(shí)現(xiàn)良好的抗SEU和MCU性能。對(duì)HGC eDRAM單元以及傳統(tǒng)的基于6T SRAM單元的抗輻射加固方案進(jìn)行了對(duì)比分析,結(jié)果表明HGCeDRAM單元能夠?qū)崿F(xiàn)良好的抗輻射加固性能,同時(shí)具有較小的存儲(chǔ)單元面積。第三,提出一種降低刷新功耗的自適應(yīng)刷新周期(Adaptive Refresh Period:ARP)控制系統(tǒng)。研究了HGC eDRAM的靜態(tài)功耗和刷新功耗,根據(jù)溫度和訪問(wèn)特性對(duì)HGCeDRAM單元數(shù)據(jù)保持時(shí)間的影響,提出一種基于Replica技術(shù)的ARP控制系統(tǒng)。采用ARP控制系統(tǒng),存儲(chǔ)器在高溫下以較高的頻率進(jìn)行刷新,在低溫下以較低的頻率進(jìn)行刷新,降低了HGC eDRAM的刷新功耗。在650C以下溫度,相比于傳統(tǒng)的固定刷新頻率的方法,將刷新功耗降低99.72%。同時(shí),ARP控制系統(tǒng)實(shí)現(xiàn)較低的探測(cè)誤差和較小的探測(cè)功耗。最后,提出一種基于分段交錯(cuò)的隱式刷新方法。為了解決傳統(tǒng)的刷新方法導(dǎo)致外部訪問(wèn)產(chǎn)生較大的延遲,以及訪問(wèn)帶寬可用率下降的問(wèn)題,提出一種分段交錯(cuò)的隱式刷新方法。分段交錯(cuò)的刷新方法避免了外部訪問(wèn)和內(nèi)部刷新的沖突,使外部訪問(wèn)能實(shí)時(shí)進(jìn)行,降低了刷新周到的訪問(wèn)延遲,同時(shí)將訪問(wèn)帶寬的可用率提高到100%。提出一種Dual-Port HGC eDRAM存儲(chǔ)器,數(shù)據(jù)帶寬增加100%,外部訪問(wèn)與內(nèi)部刷新不發(fā)生沖突,訪問(wèn)帶寬的可用率保持100%。針對(duì)分段交錯(cuò)的隱式刷新方法完成一行刷新需要二個(gè)時(shí)鐘周期的問(wèn)題,提出一種快速隱式刷新的方法。將完成整個(gè)存儲(chǔ)器Bank刷新需要的時(shí)鐘周期數(shù)降低約50%。對(duì)采用了隱式刷新方法的HGC eDRAM Bank進(jìn)行了仿真驗(yàn)證。
[Abstract]:In the space environment, resulting in a large number of electron hole pairs of high-energy particles incident to the semiconductor material, causing effects of total dose and single event effect, the electronic systems always face the threat of radiation effect. The effect of single particle in the electronic system data error, lead to the control system and the whole spacecraft fault in the electronic system of spacecraft. The influence of embedded memory chip, occupy most of the area affected by the single particle effect is most serious, is most vulnerable. The current device based on embedded 6T memory SRAM cell radiation hardening generally leads to a substantial increase in the area of memory, finally makes a substantial increase of electronic system cost and size. On the other hand, because of the ratio characteristics of the 6T SRAM unit of read and write operations, the development of the data process and the rapid decline in stability with the anti radiation. Embedded 6T SRAM based on the traditional unit There are obvious deficiencies. The memory gain cell structure based on embedded memory against radiation is studied, the main results are as follows. First, put forward a total dose effect gain based on unit (Total Ionizing Dose:TID) and single event latch (Single Evnet Latchup:SEL) 4P eDRAM unit. Through the analysis of the principle of reinforcement to gain unit and character analysis of TID effect and SEL effect, put forward a new anti TID/SEL reinforcement embedded storage unit. The 4P eDRAM unit was analyzed in detail, the high threshold value (H-VT) write access tube technology, negative word line voltage technology (Negative Word Line:NWL), poor pull technology the structure and voltage (Voltage Boosting technology:VBT) to improve the memory read and write performance and data retention time. The storage unit and logic can compatible with the standard CMOS process, with The storage unit area has good storage performance and smaller. Secondly, the dual redundancy (Dual-Modular Redundant:DMR) and a column to a bit interval (Column Direction Bit-Interleaving:CDBI) the combination of SEU (Single Event Upset:SEU) and (Multiple Cell Upset:MCU) multi flip reinforcement technology. Through the study of SEU characteristics and MCU characteristics of 4P the eDRAM unit, proposed the anti DMR reinforcement of 4P eDRAM unit using DMR technology. On the MCU characteristics of HGC eDRAM DMR unit after reinforcement, proposed CDBI technology make two sub unit of HGC eDRAM unit in isolation in physics, anti MCU reinforcement. The simulation results show that the HGC eDRAM unit to linear energy the transmission value (Linear Energy Transfor:LET) is a single particle effect of 120 MeV - cm2/mg, still be able to read the correct data, SEU and MCU to achieve good resistance on HGC eDRA. The M unit and the traditional anti radiation reinforcement scheme of 6T based on SRAM elements were analyzed. The results show that the HGCeDRAM unit can achieve good radiation resistant performance, storage unit area and has smaller. Third, proposed a new adaptive reduced brush cycle refresh power (Adaptive Refresh Period:ARP) control system of static power. HGC eDRAM and refresh power, according to the effect of temperature and holding time on the data access characteristics of HGCeDRAM unit, a ARP control system based on Replica technology. Using ARP control system, storage at high temperature with high frequency refresh, refresh at lower frequencies at low temperatures, reduced power consumption refresh HGC eDRAM. Under 650C temperature, fixed refresh rate compared to the traditional, will refresh the power consumption is reduced by 99.72%. at the same time, the realization of ARP control system is relatively low The detection power detection error and smaller. Finally, put forward a kind of implicit refresh method based on piecewise staggered. In order to solve the traditional method to refresh external access to large delay, and access to available bandwidth of the rate of decline, this paper presents a kind of implicit piecewise staggered refresh method. The method avoids the cross segment refresh the external and internal refresh access conflict, so that the external real-time access, reduce the refresh and thoughtful access latency, improve the availability and access bandwidth to 100%. a Dual-Port HGC eDRAM memory, according to the number of bandwidth increases 100%, the external and internal refresh access are not in conflict, the availability of access bandwidth for 100%. implicit piecewise staggered refresh method to complete a refresh requires two clock cycles, a method is proposed to fast hidden refresh. Will complete the entire storage Ban The number of clock cycles required for the K refresh is reduced by about 50%. for the simulation verification of the HGC eDRAM Bank using the implicit refresh method.

【學(xué)位授予單位】：華中科技大學(xué)
【學(xué)位級(jí)別】：博士
【學(xué)位授予年份】：2016
【分類(lèi)號(hào)】：TP333
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本文編號(hào)：1405731