本文選題：現(xiàn)場(chǎng)可編程門(mén)陣列　切入點(diǎn)：第二代雙倍數(shù)據(jù)率　出處：《河南科技大學(xué)學(xué)報(bào)(自然科學(xué)版)》2017年05期

【摘要】：為了解決目前嵌入式液晶顯示技術(shù)中存在的顯示驅(qū)動(dòng)支持分辨率低、數(shù)據(jù)更新慢及控制靈活性差等問(wèn)題,設(shè)計(jì)了一種基于現(xiàn)場(chǎng)可編程門(mén)陣列(FPGA)的LVDS接口的液晶顯示驅(qū)動(dòng)。對(duì)數(shù)據(jù)緩存技術(shù)中數(shù)據(jù)讀寫(xiě)控制等關(guān)鍵問(wèn)題進(jìn)行了分析,研究了對(duì)液晶顯示驅(qū)動(dòng)時(shí)序和低電壓差分信號(hào)(LVDS)傳輸時(shí)序�；贔PGA構(gòu)建緩存控制模塊和顯示控制模塊,實(shí)現(xiàn)數(shù)據(jù)快速更新及LVDS接口液晶顯示屏的顯示。通過(guò)QuartusⅡ軟件,對(duì)緩存控制模塊控制時(shí)序進(jìn)行了采樣分析驗(yàn)證。驗(yàn)證結(jié)果表明:第二代雙倍數(shù)據(jù)率同步動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器(DDR2 SDRAM)在166 MHz下工作,LVDS接口液晶顯示屏分辨率為1 024 pixel×768 pixel,位寬為16 bit時(shí),數(shù)據(jù)更新率達(dá)82 MHz,且控制靈活,能夠滿(mǎn)足目前對(duì)液晶顯示驅(qū)動(dòng)的需求。
[Abstract]:In order to solve the problems existing in embedded liquid crystal display technology, such as low resolution of display driver support, slow data updating and poor control flexibility, etc. A liquid crystal display driver based on FPGA (Field Programmable Gate Array) LVDS interface is designed. The key problems such as data reading and writing control in data buffer technology are analyzed. This paper studies the timing of liquid crystal display drive and low voltage differential signal transfer. The buffer control module and display control module are constructed based on FPGA to realize the fast data updating and the display of LVDS interface liquid crystal display screen. Through Quartus 鈪，

本文編號(hào)：1687183