【摘要】：本文研究的是基于PowerPC體系結(jié)構(gòu)超標(biāo)量X型微處理器中的整數(shù)運(yùn)算單元。整數(shù)運(yùn)算單元是X型微處理器的核心單元，承擔(dān)起整個(gè)芯片關(guān)于整數(shù)的加法、乘法、除法和邏輯的運(yùn)算。因而對(duì)整數(shù)運(yùn)算單元的研究與設(shè)計(jì)有相當(dāng)重要的意義。 本文重點(diǎn)研究和設(shè)計(jì)整數(shù)運(yùn)算單元的加法器、乘法器和除法器。加法器采用的是改進(jìn)型超前進(jìn)位加法器的設(shè)計(jì)，采用組內(nèi)串行進(jìn)位，組間并行求得進(jìn)位的方法，實(shí)現(xiàn)了兩個(gè)32位整數(shù)的相加，并對(duì)進(jìn)位和求 和‖的電路進(jìn)行了優(yōu)化；乘法器采用的是改進(jìn)型的Booth編碼乘法器設(shè)計(jì)，采用的是基為4的Booth編碼，并對(duì)產(chǎn)生的部分積，采用改進(jìn)型的華萊士樹(shù)進(jìn)行壓縮，并采用反饋電路將每個(gè)周期得到的部分積迭代相加，極大加快了運(yùn)算的速度，優(yōu)化了電路；除法器采用的是基為4的不恢復(fù)余數(shù)除法器設(shè)計(jì)，每個(gè)周期處理整數(shù)的兩位相除，通過(guò)20個(gè)周期循環(huán)完成兩位32位整數(shù)的除法，在求 商‖的電路實(shí)現(xiàn)上進(jìn)行了適當(dāng)?shù)膬?yōu)化，加快了異號(hào)相除得到的商的修正運(yùn)算，在整個(gè)除法的電路上，采用循環(huán)電路的設(shè)計(jì)，雖然增加了運(yùn)算時(shí)間，但節(jié)省了大量面積和成本。 本文最后，對(duì)整數(shù)運(yùn)算單元的加法器、除法器和乘法器，，進(jìn)行了模塊級(jí)和系統(tǒng)級(jí)的驗(yàn)證，經(jīng)過(guò)對(duì)比驗(yàn)證，所設(shè)計(jì)的部分，通過(guò)了前仿和后仿，在論文的第五章，給出了最終得到的設(shè)計(jì)版圖。
[Abstract]:In this paper, the integer operation unit in superscalar X microprocessor based on PowerPC architecture is studied. Integer operation unit is the core unit of type X microprocessor, which undertakes the addition, multiplication, division and logic operation of integer in the whole chip. Therefore, it is of great significance to study and design integer operation units. In this paper, the adders, multiplier and divider of integer operation unit are studied and designed. The additive adopts the design of the improved advanced carry adder, adopts the method of serial carry in the group and gets the carry in parallel between the two groups, realizes the addition of two 32-bit integers, and optimizes the circuit of carry sum and sum. The multiplier adopts the improved Booth coding multiplier design, uses the base 4 Booth coding, and uses the improved Wallace tree to compress the generated partial product. The feedback circuit is used to add the partial product of each cycle, which greatly accelerates the operation speed and optimizes the circuit. The divider adopts the design of non-recovery remainder divider based on 4, which processes the division of two bits of integers in each cycle, and completes the division of two-bit 32-bit integers through 20 cycle cycles. The circuit realization of the quotient is properly optimized. The correction operation of quotient obtained by different sign division is speeded up. In the whole division circuit, the design of cyclic circuit is adopted, although the operation time is increased, but a lot of area and cost are saved. At the end of this paper, the adders, dividers and multiplier of integer operation unit are verified at module level and system level. after comparison and verification, the designed part passes through front imitation and post imitation, in the fifth chapter of the paper, The final design layout is given.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP332.2;TN402

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本文編號(hào)：2491895