基于EJTAG的OCD調(diào)試方案的研究與實現(xiàn)
發(fā)布時間：2019-05-22 04:16
【摘要】：隨著我國集成電路技術(shù)的不斷發(fā)展，越來越多由我國自主研發(fā)的國產(chǎn)SoC芯片出現(xiàn)在市場當中。本課題的研究對象SoC CPU Core就是由我國研發(fā)的一款兼容MIPS32的處理器核，其主要面向的是數(shù)字電視、機頂盒設備、網(wǎng)絡設備、存儲設備及消費類電子產(chǎn)品市場。該SoC CPU的研制成功標志著我國在微處理器的設計方面實現(xiàn)了重大突破，并且打破了我國長期依賴于外國處理器的現(xiàn)狀。但是對于該SoC CPU而言，國內(nèi)選擇使用該款CPU的廠商并不多。而一款CPU要想大規(guī)模地推廣開來，CPU廠商對其開發(fā)工具的支持要足夠強大，CPU廠商必須提供穩(wěn)定地開發(fā)工具鏈。而這其中調(diào)試器的作用尤其重要，因為在嵌入式SoC芯片的設計開發(fā)過程中，采用一種高效而穩(wěn)定的調(diào)試方案有助于降低芯片的開發(fā)難度，能夠幫助開發(fā)人員快速定位問題所在，從而大大縮短芯片的開發(fā)周期。然而國內(nèi)對SoC CPU的片上調(diào)試技術(shù)的研究還處于起步階段，因此本課題的研究意義極大。 本論文首先描述了嵌入式開發(fā)中的遠程調(diào)試的概念，隨后又詳細介紹了當前嵌入式領域中所采用的各種調(diào)試方案：軟件仿真調(diào)試方案、軟件插樁調(diào)試方案、ICE調(diào)試方案以及片上調(diào)試方案。本論文主要研究的是針對該SoC CPU的片上調(diào)試方案的實現(xiàn)。因此，深入研究了該SoC CPU的架構(gòu)特點，SoC CPU對調(diào)試異常的處理，調(diào)試模式下的內(nèi)存映射等內(nèi)容。本文中的SoC CPU采用的是EJTAG來支持其片上調(diào)試，片上調(diào)試方案實現(xiàn)的基礎就是EJTAG接口，所以本論文對EJTAG的工作原理進行了詳細的描述。在調(diào)試軟件的選擇上，使用GDB來作為調(diào)試主機端的調(diào)試器，，進行源碼級的調(diào)試工作。并在研究了GDB遠程調(diào)試協(xié)議RSP的基礎上，實現(xiàn)了一個調(diào)試代理，即gdb server，實現(xiàn)了GDB調(diào)試器對SoC處理器EJTAG接口的支持，從而實現(xiàn)了一個低成本、支持源碼級調(diào)試的片上調(diào)試方案。
[Abstract]:With the continuous development of integrated circuit technology in China, more and more domestic SoC chips developed by our country appear in the market. The research object of this subject, SoC CPU Core, is a MIPS32 compatible processor core developed by our country, which is mainly aimed at digital TV, set-top box equipment, network equipment, storage equipment and consumer electronic product market. The successful development of the SoC CPU marks a great breakthrough in the design of microprocessors in our country, and breaks the present situation that our country relies on foreign processors for a long time. But for the SoC CPU, there are not many domestic manufacturers who choose to use the CPU. If a CPU is to be popularized on a large scale, the support of CPU vendors for its development tools should be strong enough, and CPU vendors must provide a stable development tool chain. Among them, the debugger plays a particularly important role, because in the process of designing and developing embedded SoC chip, adopting an efficient and stable debugging scheme helps to reduce the difficulty of chip development and can help developers to locate the problem quickly. Thus, the development cycle of the chip is greatly shortened. However, the domestic research on-chip debugging technology of SoC CPU is still in its infancy, so the research of this topic is of great significance. This paper first describes the concept of remote debugging in embedded development, and then introduces in detail all kinds of debugging schemes used in the embedded field: software simulation debugging scheme, software pile debugging scheme, ICE debugging scheme and on-chip debugging scheme. This paper mainly studies the implementation of on-chip debugging scheme for the SoC CPU. Therefore, the architecture characteristics of the SoC CPU are deeply studied, such as the handling of debugging exceptions by, SoC CPU, the memory mapping in debugging mode, and so on. In this paper, SoC CPU uses EJTAG to support on-chip debugging, and the implementation of on-chip debugging scheme is based on EJTAG interface, so the working principle of EJTAG is described in detail in this paper. In the selection of debugging software, GDB is used as the debugger on the debugging host side to debug the source code level. On the basis of studying GDB remote debugging protocol RSP, a debugging agent is implemented, that is, gdb server, realizes the support of GDB debugger for SoC processor EJTAG interface, thus realizing a low cost on-chip debugging scheme which supports source code level debugging.
【學位授予單位】：中國海洋大學
【學位級別】：碩士
【學位授予年份】：2012
【分類號】：TN47;TP368.1
本文編號：2482671
[Abstract]:With the continuous development of integrated circuit technology in China, more and more domestic SoC chips developed by our country appear in the market. The research object of this subject, SoC CPU Core, is a MIPS32 compatible processor core developed by our country, which is mainly aimed at digital TV, set-top box equipment, network equipment, storage equipment and consumer electronic product market. The successful development of the SoC CPU marks a great breakthrough in the design of microprocessors in our country, and breaks the present situation that our country relies on foreign processors for a long time. But for the SoC CPU, there are not many domestic manufacturers who choose to use the CPU. If a CPU is to be popularized on a large scale, the support of CPU vendors for its development tools should be strong enough, and CPU vendors must provide a stable development tool chain. Among them, the debugger plays a particularly important role, because in the process of designing and developing embedded SoC chip, adopting an efficient and stable debugging scheme helps to reduce the difficulty of chip development and can help developers to locate the problem quickly. Thus, the development cycle of the chip is greatly shortened. However, the domestic research on-chip debugging technology of SoC CPU is still in its infancy, so the research of this topic is of great significance. This paper first describes the concept of remote debugging in embedded development, and then introduces in detail all kinds of debugging schemes used in the embedded field: software simulation debugging scheme, software pile debugging scheme, ICE debugging scheme and on-chip debugging scheme. This paper mainly studies the implementation of on-chip debugging scheme for the SoC CPU. Therefore, the architecture characteristics of the SoC CPU are deeply studied, such as the handling of debugging exceptions by, SoC CPU, the memory mapping in debugging mode, and so on. In this paper, SoC CPU uses EJTAG to support on-chip debugging, and the implementation of on-chip debugging scheme is based on EJTAG interface, so the working principle of EJTAG is described in detail in this paper. In the selection of debugging software, GDB is used as the debugger on the debugging host side to debug the source code level. On the basis of studying GDB remote debugging protocol RSP, a debugging agent is implemented, that is, gdb server, realizes the support of GDB debugger for SoC processor EJTAG interface, thus realizing a low cost on-chip debugging scheme which supports source code level debugging.
【學位授予單位】：中國海洋大學
【學位級別】：碩士
【學位授予年份】：2012
【分類號】：TN47;TP368.1
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