【摘要】：本文由自動(dòng)測(cè)試系統(tǒng)(Automatic Test System,ATS)開發(fā)和SRAM(靜態(tài)隨機(jī)讀寫存儲(chǔ)器)內(nèi)建測(cè)試方法研究兩部分組成。首先,電子控制系統(tǒng)是某型號(hào)大型電子裝備的核心控制部件,有必要對(duì)其進(jìn)行全面的功能、性能檢測(cè)和故障診斷等工作。目前普遍采用內(nèi)建測(cè)試(Built in Test,BIT)技術(shù)和自動(dòng)測(cè)試(Automatic Test,AT)技術(shù)開展電子產(chǎn)品的可測(cè)試性工作。然而,該技術(shù)面臨故障檢測(cè)率(FaultDetection Rate,FDR)低、故障虛警率(Fault Alarm Rate,FAR)高等問題,嚴(yán)重降低其診斷結(jié)果的可信度。因此,在第二部分進(jìn)行了對(duì)SRAM內(nèi)建測(cè)試方法的深入研究,從故障模型和測(cè)試算法研究與優(yōu)化入手,改進(jìn)測(cè)試算法使其能檢測(cè)出更多的SRAM故障。除此之外,可測(cè)試性工作通常由各科研單位獨(dú)立研制,缺乏統(tǒng)一性、規(guī)范性和通用性。因此,在充分考慮現(xiàn)狀之后,本文開展以下研究工作:(1)以往的測(cè)試方法是根據(jù)硬件電路的可測(cè)試點(diǎn)建立測(cè)試項(xiàng)目,然而該方法不具有通用性且測(cè)試覆蓋率較低。本文將電子控制系統(tǒng)劃分為六大功能模塊,并分析各功能模塊的故障模型、BIT設(shè)計(jì)特點(diǎn),為其建立內(nèi)建測(cè)試項(xiàng)目。(2)在集成CPCI板卡的自動(dòng)測(cè)試設(shè)備上開發(fā)自動(dòng)測(cè)試系統(tǒng)上位機(jī)平臺(tái),以衡量BIT對(duì)電子產(chǎn)品故障診斷能力。同時(shí),為了減少同類自動(dòng)測(cè)試設(shè)備的開發(fā)周期、成本以及提高軟件后期維修和維護(hù)便利性,開發(fā)類驅(qū)動(dòng)接口層軟件,分離了上層界面和底層驅(qū)動(dòng),此方法具有較好的可移植性。(3)針對(duì)故障檢測(cè)率低的問題,本文將研究重心轉(zhuǎn)移到存儲(chǔ)器故障檢測(cè)上。由于存儲(chǔ)器成為SoC中極為重要的組成部分且存儲(chǔ)器在SoC占據(jù)極高的面積比例,本文重點(diǎn)針對(duì)存儲(chǔ)器之一的靜態(tài)隨機(jī)讀寫存儲(chǔ)器(Static Random Access Memory,SRAM)故障模型及其測(cè)試算法進(jìn)行深入研究,并針對(duì)每一種單一故障和耦合故障總結(jié)其最簡測(cè)試算法,經(jīng)過合并優(yōu)化,然后推導(dǎo)出具有較高故障檢測(cè)率的MarchC-SOF+算法。提高SRAM的故障檢測(cè)率從而提高整個(gè)電子控制系統(tǒng)的故障檢測(cè)率。(4)使用VerilogHDL語言對(duì)SRAM的測(cè)試電路進(jìn)行硬件語言描述,同時(shí)引入片選信號(hào)電路和門控時(shí)鐘邏輯電路用以降低芯片功耗,并在ISE和ISE ChipScope平臺(tái)上進(jìn)行理論仿真和實(shí)驗(yàn)驗(yàn)證,以驗(yàn)證該方法的可行性以及在故障檢測(cè)率方面的改善。
[Abstract]:This paper consists of two parts: (Automatic Test System,ATS (automatic test system) development and SRAM (static random access memory) built-in test method. First of all, the electronic control system is the core control component of a large electronic equipment, it is necessary to carry on the comprehensive function, the performance detection and the fault diagnosis and so on to the electronic control system. At present, built-in testing (Built in Test,BIT) technology and automatic testing (Automatic Test,AT) technology are widely used to carry out the testability of electronic products. However, this technique faces the problems of low fault detection rate (FaultDetection Rate,FDR) and high false alarm rate (Fault Alarm Rate,FAR), which seriously reduces the reliability of its diagnosis results. Therefore, in the second part, in-depth study of SRAM built-in testing methods, from the fault model and test algorithm research and optimization, improved testing algorithm to detect more SRAM faults. In addition, testability work is usually developed independently by scientific research institutes, lacking unity, standardization and generality. Therefore, after taking full account of the present situation, this paper carries out the following research work: (1) the former test method is based on the hardware circuit testable point to establish the test project, however, this method is not universal and the test coverage is low. In this paper, the electronic control system is divided into six functional modules, and the fault model of each functional module and the characteristics of BIT design are analyzed. To establish the built-in test project, (2) to develop the upper computer platform of the automatic test system based on the integrated CPCI board to measure the ability of BIT to diagnose the fault of electronic products. At the same time, in order to reduce the development cycle, cost and improve the convenience of maintenance and maintenance of the same kind of automatic test equipment, the class driver interface layer software is developed, and the upper interface and the bottom driver are separated. This method has good portability. (3) in order to solve the problem of low fault detection rate, the research focus is shifted to memory fault detection. Because memory is a very important part of SoC and the memory occupies a very high area ratio in SoC, this paper focuses on the static random access memory (Static Random Access Memory,), which is one of the memory. SRAM) fault model and its test algorithm are studied deeply, and the simplest test algorithm is summarized for each single fault and coupling fault. After combining and optimizing, the MarchC-SOF algorithm with high fault detection rate is deduced. Improve the fault detection rate of SRAM and improve the fault detection rate of the whole electronic control system. (4) using Verilog HDL language to describe the test circuit of SRAM with hardware language. At the same time, chip-selected signal circuit and gated clock logic circuit are introduced to reduce the power consumption of the chip. Theoretical simulation and experimental verification are carried out on ISE and ISE ChipScope platforms to verify the feasibility of this method and the improvement of fault detection rate.
【學(xué)位授予單位】：北京交通大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TP273;TP274;TP333

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本文編號(hào)：2441533