【摘要】：飛行試驗(yàn)在飛行器的設(shè)計(jì)制造過程中是非常重要的一個(gè)環(huán)節(jié)。在飛行試驗(yàn)中,各種狀態(tài)參數(shù)信號(hào)需要實(shí)時(shí)記錄,通過分析數(shù)據(jù)來對(duì)飛行器的性能和技術(shù)指標(biāo)進(jìn)行評(píng)估和改進(jìn)。并且飛行過程中試驗(yàn)環(huán)境復(fù)雜惡劣,這對(duì)記錄數(shù)據(jù)的高速數(shù)據(jù)記錄儀的設(shè)計(jì)提出了很高的要求。本文通過細(xì)致分析高速數(shù)據(jù)記錄儀的需求,對(duì)國內(nèi)外現(xiàn)狀進(jìn)行調(diào)研,給出了高速數(shù)據(jù)記錄儀的設(shè)計(jì)方案,并對(duì)其中關(guān)鍵的硬件模塊、軟件結(jié)構(gòu)和關(guān)鍵要點(diǎn)進(jìn)行了進(jìn)一步的說明。設(shè)計(jì)采用TI公司的一對(duì)串化解串芯片來實(shí)現(xiàn)LVDS(Low Voltage Differential Signal)信號(hào)的收發(fā),在鏈路中間添加電纜均衡器,采取設(shè)計(jì)手段隔離信號(hào)地和參考地,使用兩路獨(dú)立SMA(SMall A-type)接口實(shí)現(xiàn)阻抗匹配,使得LVDS傳輸距離提高至10m以上。數(shù)據(jù)串行傳輸速率最高達(dá)到300Mbps。設(shè)計(jì)中采用2片F(xiàn)PGA控制2套硬件存儲(chǔ)電路,增加信息記錄和索引模塊,設(shè)計(jì)前端高速緩存電路,實(shí)現(xiàn)高速數(shù)據(jù)讀取。并對(duì)如何實(shí)現(xiàn)FPGA間數(shù)據(jù)通訊協(xié)同,進(jìn)行了說明。設(shè)計(jì)采用Micron公司的單片32GB的SLC(Single Level Cell)型NANDFlash作為存儲(chǔ)介質(zhì),8片并聯(lián)組成陣列實(shí)現(xiàn)256GB存儲(chǔ)。2片一組共四組,實(shí)時(shí)存儲(chǔ)速率達(dá)到50MB/s,滿足最高數(shù)據(jù)傳輸速率和數(shù)據(jù)容量的需求。高速數(shù)據(jù)記錄儀的設(shè)計(jì)符合技術(shù)指標(biāo),并且通過了環(huán)境試驗(yàn)驗(yàn)證,在暗室測(cè)試、水平掛飛、高速俯沖以及飛行試驗(yàn)中,各項(xiàng)性能指標(biāo)正常,數(shù)據(jù)記錄可靠,滿足使用流程要求。
[Abstract]:Flight test is a very important part in the design and manufacture of aircraft. In flight test, the signals of various state parameters need to be recorded in real time, and the performance and technical indexes of the aircraft are evaluated and improved by analyzing the data. And the test environment is complex and bad during flight, which requires the design of high speed data recorder to record data. By analyzing the demand of high speed data recorder and investigating the present situation at home and abroad, the design scheme of high speed data recorder is given in this paper, and the key hardware module, software structure and key points are further explained. In this paper, a pair of serial chips of TI Company are used to realize the transceiver of LVDS (Low Voltage Differential Signal) signal, the cable equalizer is added in the middle of the link, and the design method is adopted to isolate the signal ground and reference ground. Two independent SMA (SMall A-type) interfaces are used to realize impedance matching, which increases the transmission distance of LVDS to more than 10 m. The data serial transmission rate is up to 300 Mbps. In the design, two sets of hardware storage circuits are controlled by two pieces of FPGA, the information recording and indexing modules are added, the front-end cache circuit is designed, and the high-speed data reading is realized. And how to realize the data communication cooperation between FPGA is explained. In this paper, Micron's 32GB SLC (Single Level Cell) NANDFlash is used as storage medium, and 8 parallel arrays are used to realize 256GB storage. Two pieces are divided into four groups, and the real time storage rate is 50 MB / s. To meet the maximum data transmission rate and data capacity requirements. The design of the high-speed data recorder accords with the technical specifications, and has passed the environmental test verification. In the dark room test, the horizontal hanging flight, the high speed dive and the flight test, each performance index is normal, the data record is reliable, meets the use flow request.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2018
【分類號(hào)】：V217;TP333

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本文編號(hào)：2418250