相變存儲器單元高速擦寫測試方法研究
發(fā)布時間：2018-11-07 14:38
【摘要】：相變存儲器是一種新型固態(tài)非易失性存儲器，它的存儲單元面積較小，并且有進一步小型化的潛力，適合制造大容量固態(tài)存儲器。另外它的擦寫速度很快，目前已經(jīng)開始量產(chǎn)的相變存儲器芯片工作速度較閃存芯片平均快10倍以上。擦寫速度是存儲器的一項關鍵性能指標,相變存儲器在很寬的脈沖寬度范圍內都可以實現(xiàn)擦寫操作，在良好的工藝條件和測試條件下，相變存儲器單元的SET和RESET脈沖寬度可以到納秒級，RESET脈沖寬度更是可以降到1ns以下，開展相變存儲器單元的高速擦寫特性研究對拓展相變存儲器的應用領域具有重要的意義。 本文的重點是研究相變存儲器單元在皮秒RESET電脈沖作用下的非晶化行為。首先研究了高頻測量中的測試系統(tǒng)帶寬和信號完整性對測試的影響，并設計了相變存儲器單元的高速擦寫特性測試電路，分別測試了相變材料層厚度為50nm、100nm、150nm的三組相變存儲器單元樣品的皮秒RESET操作特性，實現(xiàn)了最短脈沖寬度為0.2ns的重復RESET操作。針對存儲單元陣列規(guī)模的拓展，同時為了提高測試的效率，，設計并研制了一套相變存儲器陣列高速擦寫特性測試系統(tǒng)，該測試系統(tǒng)硬件部分包括半導體特性測試儀、皮秒脈沖發(fā)生器、數(shù)字示波器、編譯碼模塊、驅動模塊、單穩(wěn)態(tài)觸發(fā)延時模塊和高速脈沖信號通道等;軟件部分為C語言程序，運行在半導體特性測試儀內置的計算機上。測試系統(tǒng)各部分通過GPIB電纜連接，測試系統(tǒng)整體具有高速脈沖信號通道帶寬大，測量精確、使用方便的優(yōu)點。 本文還利用SPICE建模對高速脈沖測試電路進行了時域瞬態(tài)仿真，驗證了高速脈沖測試方案。并研究了在皮秒電壓脈沖作用下相變材料的非晶化的機理,認為其非晶化是不依賴熱量的產(chǎn)生。提出了局部強電場引發(fā)材料內部出現(xiàn)沖擊電離的模型，較合理地解釋了相變材料在皮秒脈沖作用下的非晶化相變現(xiàn)象。
[Abstract]:Phase change memory (PCM) is a new type of solid state nonvolatile memory. Its storage cell area is small, and it has the potential of further miniaturization, so it is suitable for manufacturing large capacity solid state memory. In addition, its writing speed is very fast, and the phase-change memory chip, which has already been produced in mass production, works more than 10 times faster than the flash memory chip on average. Writing speed is a key performance index of memory. Phase change memory can be used in a wide pulse width range, under good process conditions and test conditions, The pulse width of SET and RESET can reach nanosecond order and the width of RESET pulse can be reduced to less than 1ns. It is of great significance to develop the high-speed erasure characteristics of phase-change memory cell in order to expand the application field of phase-change memory. The emphasis of this paper is to study the amorphous behavior of phase change memory cells under the action of picosecond RESET electric pulse. In this paper, the influence of the bandwidth and signal integrity of the high frequency measurement system on the test is studied, and the high speed erasure characteristic test circuit of the phase change memory cell is designed. The thickness of the phase change material layer is measured to be 50 nm / 100 nm, respectively. The picosecond RESET operation characteristics of three groups of phase change memory cell samples in 150nm are used to realize the repeated RESET operation with the shortest pulse width being 0.2ns. Aiming at the expansion of memory cell array scale, and in order to improve the efficiency of testing, a high speed erasure characteristic test system of phase change memory array is designed and developed. The hardware part of the test system includes semiconductor characteristic tester. Picosecond pulse generator, digital oscilloscope, code and decode module, drive module, Monostable trigger delay module and high-speed pulse signal channel. The software part is C language program, running on the computer built in the semiconductor characteristic tester. Each part of the test system is connected by GPIB cable. The whole test system has the advantages of high speed pulse signal channel bandwidth, accurate measurement and convenient use. The time domain transient simulation of high speed pulse test circuit is carried out by using SPICE modeling, and the scheme of high speed pulse test is verified. The mechanism of non-crystallization of phase change material under picosecond voltage pulse is studied. It is considered that the non-crystallization of phase change material is heat independent. A model of shock ionization in the materials initiated by local strong electric field is proposed. The phenomenon of amorphous phase transition of phase change materials under picosecond pulse is explained reasonably.
【學位授予單位】：華中科技大學
【學位級別】：碩士
【學位授予年份】：2012
【分類號】：TP333
本文編號：2316670
[Abstract]:Phase change memory (PCM) is a new type of solid state nonvolatile memory. Its storage cell area is small, and it has the potential of further miniaturization, so it is suitable for manufacturing large capacity solid state memory. In addition, its writing speed is very fast, and the phase-change memory chip, which has already been produced in mass production, works more than 10 times faster than the flash memory chip on average. Writing speed is a key performance index of memory. Phase change memory can be used in a wide pulse width range, under good process conditions and test conditions, The pulse width of SET and RESET can reach nanosecond order and the width of RESET pulse can be reduced to less than 1ns. It is of great significance to develop the high-speed erasure characteristics of phase-change memory cell in order to expand the application field of phase-change memory. The emphasis of this paper is to study the amorphous behavior of phase change memory cells under the action of picosecond RESET electric pulse. In this paper, the influence of the bandwidth and signal integrity of the high frequency measurement system on the test is studied, and the high speed erasure characteristic test circuit of the phase change memory cell is designed. The thickness of the phase change material layer is measured to be 50 nm / 100 nm, respectively. The picosecond RESET operation characteristics of three groups of phase change memory cell samples in 150nm are used to realize the repeated RESET operation with the shortest pulse width being 0.2ns. Aiming at the expansion of memory cell array scale, and in order to improve the efficiency of testing, a high speed erasure characteristic test system of phase change memory array is designed and developed. The hardware part of the test system includes semiconductor characteristic tester. Picosecond pulse generator, digital oscilloscope, code and decode module, drive module, Monostable trigger delay module and high-speed pulse signal channel. The software part is C language program, running on the computer built in the semiconductor characteristic tester. Each part of the test system is connected by GPIB cable. The whole test system has the advantages of high speed pulse signal channel bandwidth, accurate measurement and convenient use. The time domain transient simulation of high speed pulse test circuit is carried out by using SPICE modeling, and the scheme of high speed pulse test is verified. The mechanism of non-crystallization of phase change material under picosecond voltage pulse is studied. It is considered that the non-crystallization of phase change material is heat independent. A model of shock ionization in the materials initiated by local strong electric field is proposed. The phenomenon of amorphous phase transition of phase change materials under picosecond pulse is explained reasonably.
【學位授予單位】：華中科技大學
【學位級別】：碩士
【學位授予年份】：2012
【分類號】：TP333
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本文編號：2316670
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