發(fā)布時間：2018-11-02 15:45

【摘要】：隨著半導體工藝的發(fā)展,片上存儲器的設計容量和復雜度日益增長,傳統(tǒng)的功能驗證方法面臨著驗證完備性、可重用性、效率和可靠性等方面挑戰(zhàn).針對自主設計的某16路SIMD結構的大容量向量存儲器(vector memory,VM)覆蓋率驅動的驗證方法進行研究,基于SystemVerilog驗證方法學,采用層次化建模方法搭建了高效的VM驗證平臺,在較高抽象層次上實現(xiàn)了帶約束的隨機激勵,結合SVA斷言技術對向量存儲器向量讀訪存流水線的同步與提交狀態(tài)實時監(jiān)控,保證了關鍵時序邏輯功能驗證的完備性、正確性,有效提高了驗證效率.最終模塊級驗證結果表明,定向激勵和隨機激勵相結合能較快達到理想的代碼覆蓋率.
[Abstract]:With the development of semiconductor technology, the design capacity and complexity of on-chip memory are increasing day by day. Traditional functional verification methods face challenges of completeness, reusability, efficiency and reliability. In this paper, a self-designed verification method for a 16-channel SIMD structure with mass capacity vector memory (vector memory,VM) coverage driven is studied. Based on the SystemVerilog verification methodology, an efficient VM verification platform is built by using hierarchical modeling method. At a higher level of abstraction, the constrained random excitation is realized, and the synchronization and submission state of vector memory read and access pipeline is monitored in real time with SVA assertion technology, which ensures the completeness and correctness of the verification of key temporal logic functions. The efficiency of verification is improved effectively. The final modular level verification results show that the combination of directional excitation and random excitation can achieve an ideal code coverage quickly.
【作者單位】： 國防科學技術大學計算機學院;
【基金】：國家自然科學基金項目(61303065) 國防科學技術大學科研計劃基金項目(JC13-06-02) 教育部高等學校博士學科點專項科研基金項目(20134307120028)
【分類號】：TP333

【相似文獻】

相關期刊論文 前10條

1 鐘文楓;;下一代芯片設計與驗證語言：SystemVerilog(驗證篇)[J];電子設計應用;2008年12期

2 閆濤;申志飛;易茂祥;梅春雷;;基于SystemVerilog的I~2C總線模塊驗證[J];電子科技;2011年12期

3 ;[J];;年期

4 ;[J];;年期

5 ;[J];;年期

6 ;[J];;年期

7 ;[J];;年期

8 ;[J];;年期

9 ;[J];;年期

10 ;[J];;年期

，

本文編號：2306225