【摘要】：隨著社會的發(fā)展和信息量的增加，，人們對信息存儲系統(tǒng)速度和容量的需求不斷提升，對數(shù)據(jù)傳輸?shù)乃俣群涂煽啃砸蔡岢隽烁叩囊�。傳統(tǒng)的并行傳輸方式由于存在時鐘和數(shù)據(jù)間偏移，PCB布線難度大，信號間串擾嚴重等問題，已很難滿足高速系統(tǒng)的要求。而高速串行傳輸技術憑借其帶寬大、抗干擾性強和接口簡單等優(yōu)勢，正迅速取代傳統(tǒng)的并行技術，成為業(yè)界的主流。尤其是串行傳輸技術與現(xiàn)場可編程門陣列（FPGA）技術的結合，使得串行接口的設計變得更為簡單和靈活。 本文利用Xilinx公司Virtex-4系列FPGA中的串行接口模塊RocketIO MGT為主要數(shù)據(jù)傳輸手段，設計了一個高速視頻流存儲系統(tǒng)。該系統(tǒng)以Virtex-4系列FPGAXC4VFX100、ADSP BF537和NAND Flash K9NCG08U5M為核心器件，能夠對并行LVDS接口、Fibre Channel4X光纖接口和Camera Link高速相機接口輸入的高速數(shù)據(jù)進行實時的存儲，并能通過另一個Fibre Channel4X光纖接口對存儲數(shù)據(jù)進行高速的下載，該系統(tǒng)同時還具有檢測壞塊的功能和規(guī)避壞塊的設計。此外，本文還對系統(tǒng)的關鍵部分進行了必要的仿真，以驗證設計的可行性。
[Abstract]:With the development of the society and the increase of the amount of information, the demand for the speed and capacity of the information storage system is increasing, and the speed and reliability of the data transmission are also required. Because of the clock and data offset, the difficulty of PCB routing and the serious crosstalk between signals, the traditional parallel transmission mode is difficult to meet the requirements of high-speed systems. The high-speed serial transmission technology, with its advantages of large bandwidth, strong anti-jamming and simple interface, is rapidly replacing the traditional parallel technology and becoming the mainstream of the industry. Especially the combination of serial transmission technology and field programmable gate array (FPGA) technology makes the design of serial interface more simple and flexible. In this paper, a high speed video stream storage system is designed by using the serial interface module RocketIO MGT in Virtex-4 series FPGA of Xilinx Company as the main means of data transmission. With Virtex-4 series FPGAXC4VFX100,ADSP BF537 and NAND Flash K9NCG08U5M as the core devices, the system can store the high speed data input from parallel LVDS interface, Fibre Channel4X fiber interface and Camera Link high speed camera interface in real time. It can download the stored data at high speed through another Fibre Channel4X fiber interface. The system also has the function of detecting bad blocks and avoiding the design of bad blocks. In addition, the key parts of the system are simulated to verify the feasibility of the design.
【學位授予單位】：西安電子科技大學
【學位級別】：碩士
【學位授予年份】：2012
【分類號】：TP333

【參考文獻】

相關期刊論文 前5條

1 鄧焰,戎蒙恬;基于FPGA的3.125Gbits串行通道設計實驗[J];電子工程師;2004年11期

2 楊剛,周宗儀;基于Rocket I/O模塊的高速I/O設計[J];電子技術應用;2004年06期

3 高世杰;吳志勇;;基于RocketIO的多路相機數(shù)據(jù)傳輸系統(tǒng)的設計[J];光通信技術;2008年05期

4 孫明琪;李范鳴;;基于RocketIO的高速光纖紅外圖像串行傳輸?shù)膶崿F(xiàn)[J];科學技術與工程;2008年12期

5 林振華;;基于PCI-X和RocketIO的高速數(shù)據(jù)傳輸系統(tǒng)設計[J];現(xiàn)代雷達;2011年06期

相關碩士學位論文 前2條

1 王建軍;高速串行接口電路的研究與設計[D];國防科學技術大學;2006年

2 康瓊;基于FPGA的高速串行接口模塊仿真設計[D];西安電子科技大學;2009年

本文編號：2287006