【摘要】：當前，多核DSP是DSP技術發(fā)展的趨勢。本課題源于自主研制的一款異構(gòu)多核DSP芯片（X-QDSP）。該芯片由4個DSP核+1個RISC核組成，支持高速定浮點運算，具有EDMA、外部存儲器、多通道緩沖串口和圖形圖像加速等多個外設。EDMA控制器作為控制多個內(nèi)核與外設之間數(shù)據(jù)傳輸?shù)年P鍵部件，設計并實現(xiàn)滿足多核DSP數(shù)據(jù)高速傳輸?shù)腅DMA控制器成為本文的主要研究內(nèi)容。 1、深入研究了X-QDSP芯片的總體架構(gòu)和性能的需求，通過對EDMA工作原理的分析，設計了滿足該款DSP芯片需求的EDMA總體結(jié)構(gòu)，并完成了對各個子模塊的功能定義和詳細設計。 2、每個DSP核分配了兩個通用通道，每個通用通道由物理通道和邏輯通道組成。邏輯通道實現(xiàn)EDMA的啟動，并支持參數(shù)連接、通道鏈接和參數(shù)RAM的更新。物理通道用于生成讀寫命令，并完成讀寫命令的分離，控制方式采用并行控制機制，讀寫訪問采用流水線技術。 3、EDMA總線系統(tǒng)共有8套總線，采用讀寫總線分離的“雙總線”結(jié)構(gòu)。位寬128位的快速設備分配專用總線，慢速設備共享32位總線。仲裁機制采用固定優(yōu)先級+令牌環(huán)輪轉(zhuǎn)的策略，對來自SMC轉(zhuǎn)發(fā)CPU的請求、通用通道、專用通道的請求進行仲裁。 4、對EDMA部件進行了模塊級和系統(tǒng)級兩個層次的驗證。模塊級著重于EDMA內(nèi)部邏輯功能的實現(xiàn)。系統(tǒng)級主要驗證EDMA同多個外部設備的系統(tǒng)關系。根據(jù)對EDMA的功能分析和覆蓋率統(tǒng)計確保驗證的完備性。 經(jīng)驗證，該EDMA部件功能正確。在最壞條件下綜合，，工作主頻可達500MHz，面積1229368μm2，功耗235.8mW。
[Abstract]:At present, multi-core DSP is the development trend of DSP technology. This topic comes from a heterogeneous multi-core DSP chip (X-QDSP). The chip is composed of four DSP cores and one RISC core. It supports high speed fixed floating-point operation and has EDMA, external memory. Multi-channel buffer serial port and graphics and image acceleration, etc. EDMA controller is a key component to control data transmission between multiple cores and peripherals. The design and implementation of a EDMA controller to meet the high speed transmission of multi-core DSP data has become the main research content of this paper. 1. The overall architecture and performance requirements of X-QDSP chip are deeply studied, and the working principle of EDMA is analyzed. The overall structure of EDMA is designed to meet the requirements of the DSP chip, and the function definition and detailed design of each sub-module are completed. 2. Each DSP core allocates two common channels. Each common channel consists of physical channels and logical channels. Logical channels enable EDMA startup, and support parameter connections, channel links and parameter RAM updates. The physical channel is used to generate read / write commands, and the separation of read and write commands is completed. Parallel control mechanism is adopted in control mode, pipeline technology is used for read / write access. 3 / EDMA bus system has 8 sets of buses. The structure of "double bus" which is separated by read and write bus is adopted. The 128 bit wide fast device allocates the special bus, and the slow device shares 32 bit bus. The arbitration mechanism adopts a fixed priority token ring rotation strategy to arbitrate requests from SMC forwarding CPU, general channel, and special channel. 4. The EDMA components are verified at module level and system level. Module level focuses on the implementation of the internal logic function of EDMA. System level mainly verifies the system relationship between EDMA and multiple external devices. According to the EDMA function analysis and coverage statistics to ensure the completeness of the verification. It is proved that the function of the EDMA part is correct. Under the worst conditions, the main frequency can reach 500 MHz, the area is 1229368 渭 m ~ 2, and the power consumption is 235.8 MW.
【學位授予單位】：國防科學技術大學
【學位級別】：碩士
【學位授予年份】：2013
【分類號】：TP332

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