一種新的大容量SRAM編譯器設計
發(fā)布時間：2018-08-12 10:15
【摘要】：介紹了一種大容量的SRAM編譯器設計技術(shù)。根據(jù)SRAM容量和結(jié)構(gòu),提出了新的建模方案,并建立更優(yōu)化的時序和功耗模型。同時,根據(jù)大容量SRAM在面積和性能上的需求,選擇不同的譯碼器和拼接結(jié)構(gòu),采用合適的IP核進行拼接,并從結(jié)構(gòu)上實現(xiàn)。對512kb和1 Mb的SRAM進行了流片測試,測試結(jié)果表明,該方案對于大容量的SRAM編譯器設計是有效的。
[Abstract]:This paper introduces a large capacity SRAM compiler design technology. According to the capacity and structure of SRAM, a new modeling scheme is proposed, and a more optimized timing and power consumption model is established. At the same time, according to the demand of large capacity SRAM in area and performance, we choose different decoder and splicing structure, adopt suitable IP core to splice, and realize it from the structure. The test results of 512kb and 1Mb SRAM show that the proposed scheme is effective for large capacity SRAM compiler design.
【作者單位】： 中國科學技術(shù)大學工程科學學院;
【基金】：國家自然科學基金資助項目(61474001)
【分類號】：TP333;TP314
[Abstract]:This paper introduces a large capacity SRAM compiler design technology. According to the capacity and structure of SRAM, a new modeling scheme is proposed, and a more optimized timing and power consumption model is established. At the same time, according to the demand of large capacity SRAM in area and performance, we choose different decoder and splicing structure, adopt suitable IP core to splice, and realize it from the structure. The test results of 512kb and 1Mb SRAM show that the proposed scheme is effective for large capacity SRAM compiler design.
【作者單位】： 中國科學技術(shù)大學工程科學學院;
【基金】：國家自然科學基金資助項目(61474001)
【分類號】：TP333;TP314
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