基于32nm高性能微處理器向量控制部件的物理設計
發(fā)布時間：2018-07-28 18:23
【摘要】：通用CPU是信息產業(yè)的基礎部件，可廣泛應用在國防安全、計算機、工業(yè)控制、航空航天等重要領域。開展我國自己的通用CPU研發(fā)工作的重要性是不言而喻的。 龍芯作為我國第一款自主研發(fā)的通用CPU結束了我國無芯的歷史。而本文的研發(fā)背景正是基于龍芯最新研發(fā)的64位通用CPU龍芯3C的物理設計過程。本文詳細記述了龍芯3C向量控制部件的物理設計全過程。設計過程主要應用了Synopsys公司的物理設計規(guī)范流程，即先通過綜合軟件Design Compiler對完成改寫的代碼進行綜合優(yōu)化，得到滿足要求的門級網表。之后通過IC Compiler對設計進行詳細的布局規(guī)劃，通過解決16塊四寫四讀寄存器堆和約束標準單元的擺放位置等問題，使模塊的擁塞和時序滿足要求。在此基礎上展開時鐘樹綜合以及布線等工作。 龍芯3C面向高性能計算和服務器應用，目標工作頻率為1.25GHz，整體功耗15W。借助國際領先的32nm制造工藝以及標準的EDA設計流程，，本文設計模塊最終成功達標。
[Abstract]:General CPU is the basic part of information industry. It can be widely used in national defense security, computer, industrial control, aerospace and other important fields. The importance of developing our own general CPU research and development work is self-evident. As the first self-developed general purpose CPU in China, Godson has ended the history of core-less in our country. The research background of this paper is based on the physical design process of 64 bit general purpose CPU Ronson 3C. In this paper, the whole process of the physical design of the Ronson 3C vector control unit is described in detail. The design process mainly applies the physical design specification flow of Synopsys Company, that is to say, through the comprehensive software Design Compiler, the rewritten code is optimized synthetically, and the gate network table that meets the requirements is obtained. After that, the detailed layout planning of the design is carried out by IC Compiler. By solving the problems of 16 blocks of four-write and four-read register file and the placement of the constraint standard unit, the congestion and timing of the module can meet the requirements. On this basis, clock tree synthesis and cabling are carried out. Ronson 3C is designed for high performance computing and server application. The target frequency is 1.25 GHz, and the overall power consumption is 15W. With the help of international leading 32nm manufacturing process and standard EDA design process, the design module of this paper is successfully up to standard.
【學位授予單位】：西安電子科技大學
【學位級別】：碩士
【學位授予年份】：2012
【分類號】：TN402;TP332
本文編號：2151209
[Abstract]:General CPU is the basic part of information industry. It can be widely used in national defense security, computer, industrial control, aerospace and other important fields. The importance of developing our own general CPU research and development work is self-evident. As the first self-developed general purpose CPU in China, Godson has ended the history of core-less in our country. The research background of this paper is based on the physical design process of 64 bit general purpose CPU Ronson 3C. In this paper, the whole process of the physical design of the Ronson 3C vector control unit is described in detail. The design process mainly applies the physical design specification flow of Synopsys Company, that is to say, through the comprehensive software Design Compiler, the rewritten code is optimized synthetically, and the gate network table that meets the requirements is obtained. After that, the detailed layout planning of the design is carried out by IC Compiler. By solving the problems of 16 blocks of four-write and four-read register file and the placement of the constraint standard unit, the congestion and timing of the module can meet the requirements. On this basis, clock tree synthesis and cabling are carried out. Ronson 3C is designed for high performance computing and server application. The target frequency is 1.25 GHz, and the overall power consumption is 15W. With the help of international leading 32nm manufacturing process and standard EDA design process, the design module of this paper is successfully up to standard.
【學位授予單位】：西安電子科技大學
【學位級別】：碩士
【學位授予年份】：2012
【分類號】：TN402;TP332
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1 欒曉琨;基于QX多核芯片的層次化物理設計[D];國防科學技術大學;2009年
本文編號：2151209
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