【摘要】：亂序超標量處理器中廣泛存在的集總式結構已嚴重限制微處理器性能的提升。EDGE(Explicit Data Graph Execution)作為應對微處理器性能提升瓶頸的模型之一，從結構模型中摒棄了超標量中能耗大不易擴展的集總式結構。在分布式EDGE結構中，指令映射到多個分片上同時執(zhí)行。分片之間操作數傳遞需要延時從而導致性能下降。指令映射算法通過仔細權衡程序的并行度和分片間通信延時來試圖消除分片后帶來的性能損失。 TRIPS微處理器采用關鍵資源拓撲結構不對稱分布和靜態(tài)指令映射算法(SPDI, Static Placement Dynamic Issue)。這會導致ET(Execute Tile)上較大的負載不均衡和操作數網絡通信熱點，從而引起IPC下降。 本文在M5-EDGE模擬器中實現與TRIPS類似的EDGE結構，以此來研究指令動態(tài)Deep映射算法。在缺乏編譯器調度下，采用循環(huán)映射方式的Deep算法在發(fā)射寬度為1和2時IPC分別為SPDI的85%和98.3%。針對RT(Register Tile)和DT(Data-cache Tile)的拓撲位置，對Deep映射進行三種優(yōu)化：依照ET編號順序、“之”字形順序和計算甚塊全局通信跳步數之和來優(yōu)先選擇ET。在發(fā)射寬度為1時三種優(yōu)化與基本的Deep算法相比平均跳步分別減少2.63%、2.18%和4.70%，而IPC分別提升1.07%、1.21%和2.11%。這說明在Deep映射下優(yōu)化指令間通信跳步數能顯著提高IPC。 在Deep映射算法中，90%以上的操作數通過操作數旁路來傳遞，大大減少操作數網絡的負載。在bypass寬度為2倍發(fā)射寬度時，，本地的操作數傳遞延時幾乎下降為0。增加本地bypass寬度，能有效的減少操作數傳遞的延時。 將RT按編號分配到ET上，基本Deep映射算法的IPC提升1.77%。針對DT位置進行優(yōu)化，優(yōu)先選擇靠近DT的ET和計算甚塊通信跳數之和選擇ET。這兩種優(yōu)化比基本Deep映射IPC分別提升1.17%和1.89%。將RT和DT平鋪到ET中形成4x4的拓撲結構。在發(fā)射寬度為1和2時該結構中Deep映射的IPC分別為SPDI的97.18%和113.42%。計算跳步數選擇ET，這一比值為97.32%和114.06%。微結構變化導致拓撲距離變小或者Deep映射算法優(yōu)化通信跳步數時，能顯著提高系統(tǒng)IPC。
[Abstract]:The lumped structure widely existing in scrambled superscalar processors has seriously restricted the performance improvement of microprocessors. Edge (Explicit Data Graph Execution) is one of the models to deal with the bottleneck of microprocessor performance enhancement. The lumped structure with large energy consumption in superscalar is abandoned from the structural model. In a distributed EDGE architecture, instructions are mapped to multiple slices to execute simultaneously. The transmission of operands between slices requires delay, which results in performance degradation. The instruction mapping algorithm tries to eliminate the performance loss caused by fragmentation by carefully weighing the program parallelism and inter-slice communication delay. The TRIPS microprocessor adopts asymmetric distribution of critical resource topology and static reference. Mapping algorithm (SPDI, Static Placement Dynamic Issue). This will lead to a large load imbalance and Operand network communication hot spots on the ET (Execute Tile), thus causing a decrease in IPC. In this paper, a EDGE structure similar to TRIPS is implemented in the M5-EDGE simulator to study the instruction dynamic Deep mapping algorithm. In the absence of compiler scheduling, the Deep algorithm using cyclic mapping is 85% of SPDI and 98.3% of SPDI when the transmission width is 1 and 2, respectively. According to the topological position of RT (Register Tile) and DT (Data-cache Tile), three kinds of optimization of Deep mapping are carried out: according to the order of et numbering, the glyph order of "its" and the sum of calculating the number of leapfrogging steps in the global communication of very block to select ETs first. When the launch width is 1, the average jump steps of the three optimizations are 2.63% and 4.70% less than those of the basic Deep algorithm, respectively, while the IPC increases by 1.07% and 2.11%, respectively. This shows that optimizing the jump number of inter-instruction communication under Deep mapping can significantly increase the number of jump steps. In the Deep mapping algorithm, more than 90% of the operands are transferred by the optograph bypass, which greatly reduces the load of the operands network. When the bypass width is 2 times the transmit width, the local Operand transfer delay is almost reduced to 0. 0. Increasing the local bypass width can effectively reduce the delay of Operand transfer. RT is assigned to et by number, and the IPC of basic Deep mapping algorithm increases by 1.77. For the DT position optimization, the et near DT and the sum of calculated VBS hops are selected first. These two optimizations are 1.17% and 1.89% higher than the basic Deep mapping IPC, respectively. The RT and DT are tiled into the et to form the topological structure of 4x4. When the emission width is 1 and 2, the IPC of Deep map is 97.18% of SPDI and 113.42% of SPDI, respectively. The ratio of ETs was 97.32% and 114.06% respectively. When the topology distance becomes smaller or the Deep mapping algorithm optimizes the number of communication hops, the system IPCs can be improved significantly.
【學位授予單位】：哈爾濱工業(yè)大學
【學位級別】：碩士
【學位授予年份】：2012
【分類號】：TP332;TP301.6

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本文編號：2141553