本文選題：射頻識別 + ECC加密算法��； 參考：《復(fù)旦大學(xué)》2013年碩士論文

【摘要】：射頻識別(Radio Frequency Identification, RFID)技術(shù)已經(jīng)在社會生活的許多方面有著廣泛的應(yīng)用。然而其所面臨的安全威脅和隱私問題也越來越引起關(guān)注。近年來,適用于RFID標(biāo)簽的各種加密算法安全也成為了研究熱點。 本文分析了應(yīng)用于RFID系統(tǒng)的橢圓曲線加密算法的研究現(xiàn)狀,描述了橢圓曲線加密算法的算法原理,設(shè)計了一款適用于RFID標(biāo)簽的橢圓曲線加密算法(Elliptic Curve Cryptography, ECC)處理器,并對安全標(biāo)簽芯片進(jìn)行了電路實現(xiàn)、FPGA驗證測試。在算法層,本文分析了ECC系統(tǒng)參數(shù)對安全性及實現(xiàn)成本的影響,確定采用投影坐標(biāo)系下二進(jìn)制擴(kuò)域上163位長度的橢圓曲線。對實現(xiàn)ECC點乘的各種算法進(jìn)行分析研究,選取了最適合RFID標(biāo)簽面積和功耗要求的Lopez-Dahab算法,并研究解決了實現(xiàn)該算法的各種難題。在電路設(shè)計方面,設(shè)計了專用的算術(shù)邏輯單元實現(xiàn)有限域上的加法、平方與乘法運算,并分別進(jìn)行了優(yōu)化。最后,為了驗證本論文中所設(shè)計的ECC處理器的正確性與性能,驗證了電路中各個算術(shù)單元的功能,采用FPGA進(jìn)行功能驗證,并在SMIC0.13工藝上完成了整個標(biāo)簽芯片的ASIC實現(xiàn)。芯片面積為0.4×0.4mmm2,在1.2V工作電壓下功耗為20μA。驗證結(jié)果表明該ECC處理器完全符合RFID標(biāo)簽功耗、面積和時序要求,達(dá)到了預(yù)期目標(biāo)。
[Abstract]:Radio Frequency Identification (RFID) technology has been widely used in many aspects of social life. However, its security threats and privacy issues have attracted more and more attention. In recent years, the security of various encryption algorithms suitable for RFID tags has also become a research hotspot. In this paper, the research status of elliptic curve encryption algorithm used in RFID system is analyzed, the principle of elliptic curve encryption algorithm is described, and an Elliptic Curve Cryptograph (ECC) processor is designed for RFID tag. The security tag chip is tested by FPGA. In the algorithm layer, the influence of ECC system parameters on security and implementation cost is analyzed, and the 163-bit elliptic curve in the binary extended field in projection coordinate system is determined. Various algorithms for implementing ECC point multiplication are analyzed and studied. Lopez-Dahab algorithm, which is the most suitable for RFID tag area and power consumption requirements, is selected, and various problems in the implementation of this algorithm are studied and solved. In the aspect of circuit design, special arithmetic logic unit is designed to realize addition, square and multiplication on finite field, and the optimization is carried out respectively. Finally, in order to verify the correctness and performance of the ECC processor designed in this paper, the functions of each arithmetic unit in the circuit are verified. FPGA is used to verify the function, and the ASIC implementation of the whole tag chip is completed in SMIC0.13 process. The chip area is 0.4 脳 0.4mmm2, and the power consumption is 20 渭 A. The verification results show that the ECC processor fully meets the RFID tag power consumption, area and timing requirements, and achieves the desired goal.
【學(xué)位授予單位】：復(fù)旦大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2013
【分類號】：TP332;TP391.44

【參考文獻(xiàn)】

相關(guān)期刊論文 前2條

1 何艷;胡建峗;閔昊;;一種基于射頻電子標(biāo)簽的超低電壓低功耗基帶處理器[J];半導(dǎo)體學(xué)報;2006年10期

2 張文新;鄧毅華;謝勝利;;基于嵌入式RFID中間件的標(biāo)簽數(shù)據(jù)處理[J];微計算機信息;2009年14期

，

本文編號：2086683