本文選題：糾錯檢錯(EDAC) + 單粒子翻轉(SEU)　； 參考：《國防科學技術大學》2012年碩士論文

【摘要】：由于受到空間輻射的影響，使得存儲器較大概率發(fā)生單粒子翻轉事件，嚴重影響了航天設備運行的可靠性。本文基于TMS320VC33平臺自主設計實現了基于FPGA的32位EDAC系統(tǒng)，當存儲器發(fā)生SEU事件時，該EDAC系統(tǒng)能夠正確實現糾1檢2功能，克服了SEU事件給星載計算機帶來的影響。 本文的主要貢獻包括： (1)研究了用于EDAC糾1檢2碼的編解碼的基本理論，對比實現了三種糾1檢2碼：(39,32)擴展Hamming碼，(39,32)Hisao碼和(40,32)SEC-DED碼，從FPGA實現的邏輯延時考慮，最終選擇(40,32)SEC-DED碼作為32位DAC系統(tǒng)的碼型設計基礎； (2)基于TMS320VC33平臺，采用Verilog HDL語言設計實現了EDAC編解碼模塊，采用子表達式共享技術優(yōu)化了EDAC譯碼邏輯；并針對SEU事件設計實現了發(fā)生1-bit錯時EDAC自動回寫功能。綜合結果表明，EDAC模塊在Actel FPGAA54SX72A的最大組合邏輯延時為22.677ns。板級測試表明，當DSP工作頻率為60MHz，DSP訪問SRAM需要1個等待時鐘周期時，EDAC模塊能夠正確完成糾1檢2和回寫功能，滿足應用需求； (3)為了進一步隱藏EDAC延時，本文嘗試了采用訪存地址預測方案對DSP訪問SRAM的地址進行預測。當DSP工作頻率為40MHz時，EDAC系統(tǒng)可以正常工作。對于具有大量順序訪存的應用程序，，采用訪存地址預測方案可降低EDAC系統(tǒng)平均訪存延時； (4)為了確保星載EDAC系統(tǒng)的高可靠性，進一步對(40,32)SEC-DED碼進行了可靠性驗證，設計了仿真測試用例。通過對仿真測試時間進行估算，提出重點對1位錯和相鄰兩位錯的情形進行測試。
[Abstract]:Due to the influence of space radiation, single particle flip event occurs in large probability of memory, which seriously affects the reliability of spaceflight equipment operation. In this paper, a 32-bit EDAC system based on FPGA is designed and implemented based on TMS320VC33 platform. When the SEU event occurs in memory, the EDAC system can correctly realize the function of correcting 1, check and 2, which overcomes the influence of SEU event on spaceborne computer. The main contributions of this paper include: In this paper, the basic theory of coding and decoding for EDAC correction 1, check and 2 codes is studied, and three kinds of rectifying 1 and 2 codes are compared and realized. The extended Hamming codes are as follows: / 39 / 32 / Hisao code and 40 / 32 / 32 / SEC-DED code. Considering the logic delay of FPGA implementation, Finally, the SEC-DED code is chosen as the design basis of 32-bit DAC system. 2) based on TMS320VC33 platform, the EDAC codec module is designed and implemented by Verilog HDL language, the EDAC decoding logic is optimized by subexpression sharing technology, and the EDAC auto-write-back function when 1-bit error occurs is designed and implemented for SEU events. The results show that the maximum combinatorial logic delay of EDAC module in Actel FPGAA54SX72A is 22.677 ns. The results of board level test show that the DSP module can correctly complete the function of correcting 1 check 2 and write back when the SRAM needs a waiting clock cycle when the frequency of DSP is 60 MHz. In order to further hide the EDAC delay, this paper attempts to use the memory access address prediction scheme to predict the DSP access SRAM address. The DSP system can work normally when the frequency of 40MHz is 40MHz. For applications with a large number of sequential memory access, the average memory access delay in EDAC system can be reduced by using the memory access address prediction scheme. In order to ensure the high reliability of spaceborne EDAC system, the reliability verification of SEC-DED code is further carried out, and a simulation test case is designed. By estimating the time of simulation test, the emphasis is put forward to test the case of one dislocation and two adjacent dislocations.
【學位授予單位】：國防科學技術大學
【學位級別】：碩士
【學位授予年份】：2012
【分類號】：TN791;TP333

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