本文選題：串行通信總線 + IP核��； 參考：《華中科技大學(xué)》2013年碩士論文

【摘要】：隨著集成電路設(shè)計(jì)發(fā)展到系統(tǒng)級(jí)的設(shè)計(jì)階段，以軟硬件協(xié)同設(shè)計(jì)、IP核復(fù)用和超深亞微米技術(shù)為支撐的SoC設(shè)計(jì)已成為當(dāng)今超大規(guī)模集成電路的發(fā)展方向。另一方面，串行通信總線以其結(jié)構(gòu)簡(jiǎn)單、節(jié)省傳輸線、成本更低等優(yōu)點(diǎn)在越來越多的芯片中得到應(yīng)用。本文設(shè)計(jì)了三種最具代表型的串行總線的可復(fù)用IP軟核，這符合SoC設(shè)計(jì)技術(shù)的發(fā)展方向，具有重要的實(shí)用價(jià)值。 1-Wire總線是Maxim全資子公司Dallas的一項(xiàng)技術(shù)，它采用單根信號(hào)線，同時(shí)傳輸時(shí)鐘和數(shù)據(jù)；I~2C總線是Philips公司推出的一種串行總線，定義了兩根雙向信號(hào)線，并支持多主機(jī)系統(tǒng)；SPI總線是由Motorola公司推出的一種同步串行外圍設(shè)備接口，只需要4條線就可以完成主、從設(shè)備全雙工同步通信。本文首先分析對(duì)比了常見的幾種串行通信總線并詳細(xì)介紹了1-Wire、I~2C和SPI這三種串行總線的標(biāo)準(zhǔn)協(xié)議，接著分別詳細(xì)敘述了三種IP軟核的設(shè)計(jì)與實(shí)現(xiàn)過程。首先根據(jù)需求制定了IP核的設(shè)計(jì)目標(biāo)，并結(jié)合協(xié)議特點(diǎn)定義了多個(gè)可配置參數(shù)以實(shí)現(xiàn)最大可復(fù)用性；接著采用自頂向下的設(shè)計(jì)方法進(jìn)行模塊劃分和接口時(shí)序的定義；然后采用Verilog語言描述實(shí)現(xiàn)了IP核各模塊的功能；最后在基于BFM的驗(yàn)證環(huán)境中進(jìn)行功能驗(yàn)證，使用FPGA進(jìn)行IP核原型驗(yàn)證，并在華宏-NEC0.35um工藝綜合實(shí)現(xiàn)。 設(shè)計(jì)的三種IP軟核采用不同的傳輸協(xié)議，但接口統(tǒng)一，且具備多個(gè)可配置參數(shù)，，通用性和可復(fù)用性好，可以廣泛地應(yīng)用于不同需求的芯片中。
[Abstract]:With the development of integrated circuit design to the stage of system-level design, SoC design, which is supported by hardware / software co-design IP core reuse and ultra-deep sub-micron technology, has become the development direction of VLSI. On the other hand, serial communication bus has been applied in more and more chips because of its simple structure, low cost and saving transmission line. In this paper, three kinds of reusable IP soft cores of serial bus are designed, which accord with the development direction of SoC design technology and have important practical value. 1-Wire bus is a technology of Dallas, a wholly owned subsidiary of Maxim. It uses single signal line, transmits clock and data at the same time, is a serial bus developed by Philips Company, and defines two two-way signal lines. The SPI bus is a synchronous serial peripheral interface developed by Motorola. It only needs 4 lines to complete the master and slave full duplex synchronous communication. In this paper, several common serial communication buses are analyzed and compared, and the standard protocols of 1-WireWay I2C and SPI are introduced in detail. Then, the design and implementation of three kinds of IP soft cores are described in detail. Firstly, the design goal of IP core is defined according to the requirements, and several configurable parameters are defined according to the characteristics of the protocol to realize the maximum reusability, then the module partition and interface timing are defined by the top-down design method. Then the functions of each module of IP core are described and implemented by Verilog language. Finally, the function verification is carried out in the verification environment based on BFM, and the prototype verification of IP core is carried out by using FPGA, which is implemented comprehensively in Huahong-NEC0.35um process. The three kinds of IP soft core adopt different transmission protocols, but the interface is uniform, and it has many configurable parameters. It has good versatility and reusability, so it can be widely used in chips with different requirements.
【學(xué)位授予單位】：華中科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP336;TN402

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本文編號(hào)：1925872