本文選題：微處理器 + 低功耗　； 參考：《國(guó)防科學(xué)技術(shù)大學(xué)》2013年碩士論文

【摘要】：隨著高性能微處理器進(jìn)入多核多線程處理器設(shè)計(jì)時(shí)代,集成電路生產(chǎn)工藝發(fā)生翻天覆地的變革,傳統(tǒng)的摩爾定律受到前所未有的挑戰(zhàn),功耗問題成為制約處理器發(fā)展的首要問題之一。尤其在集成電路制造工藝進(jìn)入90nm工藝尺寸后,漏流功耗問題愈發(fā)突出,傳統(tǒng)的低功耗技術(shù)不能有效控制漏流功耗,因此新的低功耗技術(shù)應(yīng)運(yùn)而生。本文通過對(duì)X微處理器代碼進(jìn)行研究,分析處理器結(jié)構(gòu)功能,在此基礎(chǔ)上為X微處理器增加門控電源設(shè)計(jì)以降低處理器功耗。設(shè)計(jì)針對(duì)處理器核心的粗粒度門控電源,在不需要某些處理器核工作時(shí)關(guān)閉處理器核電源。設(shè)計(jì)了一個(gè)功耗管理控制單元PMC來完成處理器核上下電流程的控制。研究門控電源技術(shù)的驗(yàn)證方法,并提出電源開關(guān)的后端設(shè)計(jì)方案。設(shè)計(jì)針對(duì)處理器SRAM的細(xì)粒度門控電源,提出一種硬件動(dòng)態(tài)控制的門控電源設(shè)計(jì)方案。本文首先為處理器合理劃分電源域,設(shè)計(jì)電源模式,完成門控電源整體方案設(shè)計(jì)。通過編寫CPF通用低功耗格式文件將設(shè)計(jì)方案施加在處理器上,并針對(duì)X微處理器核工作特點(diǎn)設(shè)計(jì)核心上下電流程方案。通過模擬驗(yàn)證說明低功耗意圖已成功部署在處理器上。根據(jù)處理器結(jié)構(gòu)特點(diǎn),為實(shí)現(xiàn)上下電流程的自動(dòng)控制本文設(shè)計(jì)了功耗管理控制單元PMC。具體介紹了PMC的設(shè)計(jì)方案,分析其結(jié)構(gòu)組成、工作原理和內(nèi)部狀態(tài)轉(zhuǎn)換,并編寫verilog代碼實(shí)現(xiàn)設(shè)計(jì)。最后通過編寫測(cè)試激勵(lì),將CPF文件同X微處理器代碼一起進(jìn)行模擬測(cè)試。通過觀察波形驗(yàn)證了PMC設(shè)計(jì)功能的正確性,能夠起到正確控制核心打開和關(guān)斷的作用。最后本文闡述了門控電源設(shè)計(jì)的驗(yàn)證方法,結(jié)合布局布線相關(guān)技術(shù),提出了門控電源網(wǎng)絡(luò)設(shè)計(jì)方法。通過對(duì)多種不同的門控電源開關(guān)結(jié)構(gòu)進(jìn)行分析對(duì)比,使用RedHawk軟件測(cè)試不同結(jié)構(gòu)的電源開關(guān)和不同鏈間上電間隔的電源開關(guān)對(duì)瞬態(tài)電流的影響,最后提出一種測(cè)試效果較好的四條鏈并聯(lián)結(jié)構(gòu)的電源開關(guān)結(jié)構(gòu)。另外,本文針對(duì)X處理器中的一級(jí)指令cache提出了硬件動(dòng)態(tài)控制的細(xì)粒度電源門控技術(shù),利用指令隊(duì)列進(jìn)行程序中循環(huán)代碼的檢測(cè)。一旦檢測(cè)到循環(huán)代碼,就可以對(duì)指令cache進(jìn)行電源門控,從而降低動(dòng)態(tài)功耗和靜態(tài)功耗。模擬實(shí)驗(yàn)數(shù)據(jù)表明,該方法不但可以降低動(dòng)態(tài)功耗和靜態(tài)功耗,還可以小幅度提升性能。
[Abstract]:With the entry of high-performance microprocessors into the era of multi-core multi-thread processor design, the production process of integrated circuits has undergone world-shaking changes, the traditional Moore's law has been unprecedented challenges. Power consumption has become one of the most important problems restricting the development of processors. Especially after the IC manufacturing process enters the 90nm process size, the leakage power problem becomes more and more prominent. The traditional low-power technology can not effectively control the leakage power consumption, so the new low-power technology emerges as the times require. In this paper, the code of X microprocessor is studied, and the structure and function of the processor are analyzed. On this basis, the design of gated power supply for X microprocessor is added to reduce the power consumption of the processor. A coarse-grained gated power supply for processor core is designed to turn off processor core power when some processor cores are not needed. A power management control unit (PMC) is designed to control the power flow of the processor core. The verification method of gated power supply technology is studied, and the back end design scheme of power switch is proposed. A hardware dynamic control scheme for a fine-grained gated power supply for processor SRAM is proposed. Firstly, this paper divides the power domain reasonably for the processor, designs the power supply mode, and completes the whole scheme design of the gated power supply. The design scheme is applied to the processor by writing the CPF general low power format file, and the core charging flow scheme is designed according to the working characteristics of the X microprocessor core. Simulation verification shows that the low power intention has been successfully deployed on the processor. According to the characteristics of processor architecture, a power management control unit (PMC) is designed to realize the automatic control of power flow. This paper introduces the design scheme of PMC, analyzes its structure, working principle and internal state transformation, and writes verilog code to realize the design. Finally, the CPF file and X microprocessor code are simulated and tested by writing test incentives. The function of PMC design is verified by observing the waveform, which can control the opening and closing of the core correctly. Finally, this paper describes the verification method of the gated power supply design, and puts forward the design method of the gated power supply network based on the layout and wiring technology. Through the analysis and comparison of many different switch structures, the influence of the power switch with different structure and the power switch between the different chains on the transient current is tested by using RedHawk software. Finally, a power switch structure with four chains parallel structure is proposed. In addition, this paper presents a fine-grained power gating technique for the first-order instruction cache in X processor, which is dynamically controlled by hardware. The instruction queue is used to detect the cyclic code in the program. Once the cyclic code is detected, the instruction cache can be power gated to reduce the dynamic and static power consumption. The simulation results show that the proposed method can not only reduce dynamic and static power consumption, but also improve performance by a small margin.
【學(xué)位授予單位】：國(guó)防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP332
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本文編號(hào)：1911207