發(fā)布時(shí)間：2018-05-03 09:37

  本文選題：OTP存儲(chǔ)器 + 電荷泵��； 參考：《電子科技大學(xué)》2012年碩士論文

【摘要】：OTP存儲(chǔ)器的功能介于Mask ROM和EPROM之間,既給用戶(hù)提供一定自由配置的空間又無(wú)需復(fù)雜的擦除機(jī)制,所以其電路結(jié)構(gòu)簡(jiǎn)單且可靠性高,被廣泛應(yīng)用于密鑰保存、嵌入式存儲(chǔ)及空間軍事應(yīng)用。論文旨在設(shè)計(jì)實(shí)現(xiàn)一款功能正確性能良好的OTP存儲(chǔ)器。 論文參考了國(guó)內(nèi)外OTP存儲(chǔ)單元的設(shè)計(jì)方案,分析了存儲(chǔ)單元的工作原理,對(duì)其結(jié)構(gòu)進(jìn)行了設(shè)計(jì)。由于編程后的特性難以在仿真上體現(xiàn),存儲(chǔ)單元在實(shí)際工藝線上進(jìn)行了流片并完成了測(cè)試。以存儲(chǔ)單元的實(shí)測(cè)結(jié)果為基礎(chǔ),討論了存儲(chǔ)器外圍電路的構(gòu)建方案。其中多維譯碼方式配合了存儲(chǔ)陣列的排布并且縮短了延遲時(shí)間；編程電路采用高壓復(fù)制型的電荷泵,在芯片內(nèi)部有選擇地產(chǎn)生編程高壓,減小了高壓信號(hào)對(duì)內(nèi)部電路和存儲(chǔ)陣列的影響；讀取電路以位線充放電過(guò)程為基礎(chǔ),具有較短讀取時(shí)間和較大的讀取閾值；片選和輸出使能模塊為更高一級(jí)系統(tǒng)對(duì)存儲(chǔ)器的調(diào)用提供了基礎(chǔ),能降低整體系統(tǒng)功耗,也和譯碼信號(hào)一起為編程和讀取過(guò)程起到了控制作用。外圍電路的邏輯功能使用Spectre仿真得到了驗(yàn)證。 電路構(gòu)建完成之后進(jìn)行了存儲(chǔ)器整體版圖的設(shè)計(jì)并在0.18μm工藝上進(jìn)行了流片。版圖設(shè)計(jì)中考慮了各類(lèi)可制造性設(shè)計(jì)問(wèn)題以提高芯片制造良率,并在關(guān)鍵信號(hào)處設(shè)置了測(cè)試點(diǎn)以供芯片測(cè)試過(guò)程中錯(cuò)誤的排查。使用Calibre驗(yàn)證了版圖設(shè)計(jì)規(guī)則和連接關(guān)系,并解決了特殊器件的網(wǎng)表提取等細(xì)節(jié)問(wèn)題。在此基礎(chǔ)上提取了寄生參數(shù)并使用Finesim工具進(jìn)行后仿真。流片后對(duì)芯片進(jìn)行了實(shí)際測(cè)試。后仿真和實(shí)測(cè)結(jié)果都表明讀寫(xiě)功能正確,電荷泵可以產(chǎn)生所需高壓完成編程過(guò)程,讀取模塊可以針對(duì)阻值較高的存儲(chǔ)單元進(jìn)行,且具有較短的讀取時(shí)間。 論文在常規(guī)商用工藝基礎(chǔ)上成功設(shè)計(jì)實(shí)現(xiàn)了一款64Kbit OTP存儲(chǔ)器芯片,功能正確、性能良好,滿(mǎn)足預(yù)期要求。
[Abstract]:The function of OTP memory lies between Mask ROM and EPROM, which not only provides users with free configuration space but also does not need complicated erasure mechanism, so its circuit structure is simple and reliable, so it is widely used in key preservation. Embedded storage and space military applications. The purpose of this paper is to design and implement a functional OTP memory with good performance. Referring to the design scheme of OTP storage cell at home and abroad, the working principle of memory cell is analyzed, and its structure is designed. Because the characteristics of the program are difficult to be realized in the simulation, the memory cell is carried out on the actual process line and the test is completed. Based on the measured results of the memory cell, the construction scheme of the memory peripheral circuit is discussed. The multidimensional decoding method is combined with the arrangement of the memory array and the delay time is shortened; the programming circuit uses a high-voltage replication-type charge pump to selectively generate the programming high voltage inside the chip. The influence of high voltage signal on internal circuit and memory array is reduced, the reading circuit is based on the charging and discharging process of bit line, and has a short reading time and a large reading threshold. The chip selection and output enable module provide the basis for the higher level system to call the memory, reduce the overall system power consumption, and together with the decoding signal, play a controlling role in the programming and reading process. The logic function of peripheral circuit is verified by Spectre simulation. After the circuit is constructed, the whole memory layout is designed and the wafer is made on 0.18 渭 m process. In the layout design, various kinds of manufacturability design problems are considered to improve the chip manufacturing yield, and the test points are set at the key signals for the error detection during the chip testing process. The rules of layout design and the connection relation are verified by Calibre, and the detailed problems such as nettable extraction of special devices are solved. On this basis, the parasitic parameters are extracted and then simulated by Finesim tool. The chip is tested after streaming. The post-simulation and measured results show that the reading and writing function is correct, the charge pump can generate the required high voltage to complete the programming process, the reading module can be carried out for the memory cell with higher resistance value, and the reading time is shorter. On the basis of conventional commercial technology, a 64Kbit OTP memory chip is successfully designed and implemented in this paper.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類(lèi)號(hào)】：TP333

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本文編號(hào)：1837978