本文選題：嵌入式硬件系統 + FPGA��； 參考：《華中科技大學》2012年碩士論文

【摘要】：隨著第六次火車提速，主要干線開始以時速200千米每小時的高速運行，火車運行控制系統安全性越來越重要，，機車之間的數據通信越來越頻繁。計算機技術在機車車輛上的應用越來越多，列車通信網絡及主動控制成為高速列車控制中不可或缺的關鍵技術。隨著微電子技術、計算機技術、數字傳輸技術的飛速發(fā)展，自行設計并實現安全穩(wěn)定列車通信網絡設備需求越來越大。 本文介紹了基于嵌入式系統的MVB和HDLC通信模塊硬件系統的設計，該系統用于實現列車通信網絡（TCN）協議規(guī)定的MVB總線數據通信和HDLC總線數據通信。該硬件系統平臺包含大容量存儲器、高性能處理器以及多種常用外圍總線接口，以此為硬件開發(fā)平臺可實現多種總線數據的交互。 論文分析火車運行環(huán)境，確定硬件系統運行的工作環(huán)境溫度范圍以及抗震性和防雷擊設計；對比不同處理器之間差異，選擇ARM作為本系統的核心處理器，設計采用FPGA+ARM硬件平臺方案；簡要說明MVB總線及HDLC總線對硬件接口的需求；論文采用大量的篇幅對系統的總體結構設計、硬件模塊設計、總線接口設計以及硬件調試進行詳盡的論述。 經過大量的分析和設計工作，本文實現MVB總線及HDLC總線單板設計工作。同時，系統通過CAN總線以及RS485總線實現與其他設備進行數據交互。本系統已順利通過項目驗收，系統工作穩(wěn)定，性能可靠，各項指標都滿足要求。
[Abstract]:With the increase of the speed of the sixth train, the main trunk lines begin to run at a high speed of 200 km / h. The safety of the train operation control system is becoming more and more important, and the data communication between locomotives is becoming more and more frequent. The application of computer technology in locomotive and rolling stock is more and more. Train communication network and active control have become the indispensable key technology in high-speed train control. With the rapid development of microelectronic technology, computer technology and digital transmission technology, the demand for designing and implementing safe and stable train communication network equipment is increasing. This paper introduces the design of the hardware system of MVB and HDLC communication module based on embedded system. The system is used to realize the MVB bus data communication and HDLC bus data communication stipulated in the train communication network. The hardware platform consists of large capacity memory, high performance processor and a variety of common peripheral bus interfaces. This hardware development platform can realize the interaction of many kinds of bus data. This paper analyzes the running environment of the train, determines the temperature range of the operating environment of the hardware system, and the design of seismic resistance and lightning protection, compares the differences between different processors, and selects ARM as the core processor of the system. The hardware platform of FPGA ARM is adopted, the requirement of MVB bus and HDLC bus for hardware interface is briefly explained, the overall structure of the system and the hardware module are designed with a large number of pages. Bus interface design and hardware debugging are discussed in detail. After a lot of analysis and design work, this paper realizes the design of MVB bus and HDLC bus single board. At the same time, the system interacts with other devices through CAN bus and RS485 bus. This system has passed the project acceptance smoothly, the system work stably, the performance is reliable, each index all satisfies the request.
【學位授予單位】：華中科技大學
【學位級別】：碩士
【學位授予年份】：2012
【分類號】：TN919.72;TP368.1

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相關期刊論文 前2條

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