本文選題：FPGA驗證 + 嵌入式處理器��； 參考：《上海交通大學》2014年碩士論文

【摘要】：隨著科技進步與發(fā)展，嵌入式處理器的應用日益廣泛，設計規(guī)模和復雜度也飛速增長。FPGA相關技術的快速發(fā)展，為嵌入式處理器的功能驗證提供技術基礎。本文旨在完成一款高性能嵌入式處理器FPGA驗證工作。 本文首先對相關內容進行研究，包括嵌入式處理器結構、芯片設計流程、功能驗證方法、FPGA驗證關鍵步驟、FPGA結構和資源等。然后，基于一款高性能CPU內核，提出并實現(xiàn)一款嵌入式處理器系統(tǒng)的硬件設計。利用豐富的FPGA資源，設計一個結構簡單、靈活通用的FPGA驗證平臺。在代碼設計階段開始搭建驗證的基本系統(tǒng)，提前開始FPGA驗證和軟件開發(fā)，提高驗證效率，增加驗證可靠性和驗證平臺利用率。 本文具體闡述了驗證平臺的實現(xiàn)過程。首先分析需求選擇可行方案，，然后介紹代碼移植過程，最后闡述基本系統(tǒng)搭建過程。以CPU核和DDR3測試為例介紹具體驗證過程。在驗證過程中，采用提前建立FPGA原型庫、腳本批量調用和修改代碼、使用多種調試方法等，努力提高可重用性和自動化程度，減少人為錯誤、提高工作效率。采用“模塊級——系統(tǒng)級——應用級”遞進式驗證步驟，運行操作系統(tǒng)和測試程序，實現(xiàn)功能驗證目標。驗證結果表明驗證平臺合理可靠、靈活通用，驗證效率高。最后，對主要工作進行總結。
[Abstract]:With the progress and development of science and technology, embedded processors are increasingly widely used, and the design scale and complexity are also growing rapidly. The rapid development of FPGA related technologies provides a technical basis for the functional verification of embedded processors. The purpose of this paper is to complete the FPGA verification of a high performance embedded processor. At first, this paper studies the related contents, including embedded processor structure, chip design flow, function verification method, FPGA verification key steps, FPGA structure and resources, and so on. Then, based on a high performance CPU kernel, the hardware design of an embedded processor system is proposed and implemented. Using abundant FPGA resources, a simple and flexible FPGA verification platform is designed. At the stage of code design, the basic system of verification is built, FPGA verification and software development are started in advance, the efficiency of verification is improved, the reliability of verification and the utilization rate of verification platform are increased. This paper describes the implementation process of the verification platform. This paper first analyzes the requirements of selecting feasible solutions, then introduces the process of code transplantation, and finally describes the process of building the basic system. Taking CPU kernel and DDR3 test as examples, the concrete verification process is introduced. In the process of verification, FPGA prototype library is built ahead of time, script batch calls and modifies code, and many debugging methods are used to improve reusability and automation, reduce human error and improve work efficiency. The function verification goal is realized by using the progressive verification step of "module level-system level-application level", running the operating system and testing program. The verification results show that the verification platform is reasonable and reliable, flexible and universal, and has high verification efficiency. Finally, the main work is summarized.
【學位授予單位】：上海交通大學
【學位級別】：碩士
【學位授予年份】：2014
【分類號】：TP332

【參考文獻】

相關期刊論文 前2條

1 楊安生;黃世震;;基于ARM SoC的FPGA原型驗證[J];電子器件;2011年03期

2 許彤;王朋宇;黃海林;范東睿;朱鵬飛;鄭保建;曹非;;嵌入式處理器在片調試功能的驗證[J];計算機輔助設計與圖形學學報;2007年04期

相關博士學位論文 前2條

1 孟建熠;超標量嵌入式處理器關鍵技術設計研究[D];浙江大學;2009年

2 殷燎;面向SoC的IP核及嵌入式處理器功能驗證方法研究[D];浙江大學;2010年

本文編號：1820966