本文選題：數(shù)字信號(hào)處理　切入點(diǎn)：流水線技術(shù)　出處：《國(guó)防科學(xué)技術(shù)大學(xué)》2014年碩士論文

【摘要】：X-DSP處理器是由國(guó)防科技大學(xué)微電子所自主研發(fā)的一款高性能64位浮點(diǎn)向量多核DSP芯片,40nm工藝下,實(shí)現(xiàn)主頻1GHz的設(shè)計(jì)目標(biāo),采用VLIW結(jié)構(gòu),40/80位變長(zhǎng)指令集,支持32/64位定點(diǎn)/浮點(diǎn)運(yùn)算,最大可支持11條標(biāo)/向量指令混合并行發(fā)射。本文以高性能X-DSP處理器的開(kāi)發(fā)與研制為背景,深入分析流水線技術(shù),設(shè)計(jì)實(shí)現(xiàn)了指令流水線上的指令派發(fā)與指令流控部件,并基于所提出的軟硬件協(xié)同驗(yàn)證平臺(tái)對(duì)系統(tǒng)級(jí)指令流水線的功能進(jìn)行驗(yàn)證。本文主要的創(chuàng)新點(diǎn)與工作內(nèi)容包括以下幾點(diǎn):1)詳細(xì)分析X-DSP處理器內(nèi)核結(jié)構(gòu)、指令格式與流水線結(jié)構(gòu)特征,進(jìn)而提出指令流水線部件中指令派發(fā)與流控部件的設(shè)計(jì)需求;2)基于超長(zhǎng)指令字(VLIW)結(jié)構(gòu),設(shè)計(jì)并實(shí)現(xiàn)可跨取指包邊界派發(fā)指令的指令派發(fā)部件,支持L1P旁路取指與仿真調(diào)試部件(ET)對(duì)流水線的控制功能;3)深入分析X-DSP分支延遲槽特征,結(jié)合對(duì)調(diào)試仿真的支持,設(shè)計(jì)并實(shí)現(xiàn)指令流控部件,完成對(duì)指令流的控制作用;4)針對(duì)指令派發(fā)與指令流控部件的邏輯設(shè)計(jì),在指令流水線系統(tǒng)級(jí)分別對(duì)其邏輯功能進(jìn)行驗(yàn)證,并完成覆蓋率分析與邏輯綜合;5)分析傳統(tǒng)FPGA原型驗(yàn)證的基本原理與不足之處,提出一種基于PLI接口的新型調(diào)試/驗(yàn)證方案:利用PLI接口實(shí)現(xiàn)C函數(shù)與Verilog的嵌套調(diào)用、采用數(shù)據(jù)共享機(jī)制實(shí)現(xiàn)不同進(jìn)程間的通信。在軟硬件協(xié)同支持下,對(duì)X-DSP的指令流水線進(jìn)行驗(yàn)證實(shí)踐,實(shí)驗(yàn)結(jié)果表明該方案使得在設(shè)計(jì)階段便可對(duì)調(diào)試接口以及流水線功能進(jìn)行更為充分的驗(yàn)證。
[Abstract]:The X-DSP processor is a high performance 64-bit floating-point vector multi-core DSP chip developed by the Institute of Microelectronics of the University of National Defense Science and Technology. Under the technology of 40nm, the design goal of the main frequency 1GHz is realized, and the 40 / 80 bit variable length instruction set is adopted in the VLIW structure. It supports 32 / 64 bit fixed-point / floating-point operation, and can support the mixed parallel transmission of 11 standard / vector instructions. In this paper, pipeline technology is deeply analyzed based on the development and research of high-performance X-DSP processor. Designed and implemented the instruction dispatch and instruction flow control unit on the instruction pipeline, Based on the proposed hardware / software co-verification platform, the function of the system-level instruction pipeline is verified. The main innovation and work contents of this paper include the following points: 1) the kernel architecture of X-DSP processor is analyzed in detail. The instruction format and pipeline structure feature, and then put forward the design requirement of instruction dispatch and flow control unit in the instruction pipeline parts. Based on the VLIW) structure, we design and implement the instruction dispatch parts that can distribute instructions across the boundary of taking the finger packet. The control function of pipeline by supporting L1P Bypass selection and Simulation debugging Unit (et) is used to analyze the characteristics of X-DSP branch delay slot in depth. Combined with the support of debugging simulation, the instruction flow control unit is designed and implemented. The logical design of instruction dispatch and instruction flow control unit is completed. The logic function of instruction pipeline is verified at the system level. The basic principles and shortcomings of traditional FPGA prototype verification are analyzed, and a new debugging / verification scheme based on PLI interface is proposed: C function and Verilog nesting call is realized by PLI interface. The data sharing mechanism is used to realize the communication between different processes. With the support of hardware and software, the instruction pipeline of X-DSP is verified. The experimental results show that the scheme can fully verify the debugging interface and pipeline function in the design stage.
【學(xué)位授予單位】：國(guó)防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類號(hào)】：TP332

【共引文獻(xiàn)】

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2 張良;異構(gòu)MPSoC下基于貪心和模擬退火算法的軟硬件劃分方法研究[D];湖南大學(xué);2013年

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本文編號(hào)：1676643