本文選題：Cache　切入點：低功耗　出處：《湖南大學》2012年碩士論文　論文類型：學位論文

【摘要】：近年來，能耗已經(jīng)成為嵌入式系統(tǒng)設計中人們關注的焦點，這主要是因為電池供電的便攜式和移動式的嵌入式產(chǎn)品的廣泛應用。高速緩沖存儲器，即Cache，是為了解決存儲器和CPU速度匹配而出現(xiàn)的。根據(jù)程序時間和空間局部性原理，在程序運行過程中，系統(tǒng)把部分數(shù)據(jù)從主存中調(diào)入到Cache，，從而CPU直接訪問Cache，減少訪問存儲器的時間。因此Cache對計算機系統(tǒng)的性能有著重要的影響。同時，Cache消耗的能量占整個處理器功耗的大部分。因此，如何降低Cache的功耗有著重大的意義。 本文詳細的分析了國內(nèi)外低功耗Cache的研究現(xiàn)狀，在可重構Cache技術的基礎上，提出了基于分支指令頻率的動態(tài)可重構Cache（BRDRC）方案和基于指令時間數(shù)的動態(tài)可重構Cache（IC-DRC）方案。動態(tài)可重構Cache技術是在程序運行過程中根據(jù)程序的需求動態(tài)的調(diào)整Cache的結構，關閉Cache中閑置未用部分的能量消耗，從而在性能損失最小的情況下，有效地降低Cache功耗。 BRDRC算法根據(jù)分支指令頻率監(jiān)測程序段是否發(fā)生變化，并確定容量調(diào)整。在程序段內(nèi)，狀態(tài)機根據(jù)動態(tài)配置策略先對Cache的關聯(lián)度進行調(diào)整，然后根據(jù)新配置下Cache的缺失率確定當前程序段Cache的最佳結構。與已有的算法相比，BRDRC算法不僅更有效地降低了Cache功耗，還大大減少了硬件開銷。 IC-DRC算法則在BRDRC算法上進行改進，根據(jù)指令時間數(shù)監(jiān)測程序段的變化，確定容量調(diào)整。在程序段內(nèi)，狀態(tài)機根據(jù)平均訪問時間對Cache的訪問進行預判，然后根據(jù)預判的結果確定當前程序段的Cache結構。預判機制的引入，不僅可以有效地避免不必要的重構，還能減少性能的損失。同時平均訪問時間比缺失率能更好的反應性能的情況。實驗結果表明，與BRDRC算法和已有算法相比，IC-DRC算法明顯地改善了性能損失，進一步的降低了Cache功耗。
[Abstract]:In recent years, energy consumption has become the focus of attention in embedded system design, which is mainly due to the widespread use of battery-powered portable and mobile embedded products. In order to solve the problem of memory and CPU speed matching, according to the principle of program time and space localization, The system transfers part of the data from main memory to Cache. so CPU can access Cachedirectly and reduce the time of accessing memory. Therefore, Cache has an important effect on the performance of computer system. At the same time, the energy consumed by Cache accounts for the power consumption of the whole processor. Most of them. So, How to reduce the power consumption of Cache has great significance. In this paper, the research status of low-power Cache at home and abroad is analyzed in detail. On the basis of reconfigurable Cache technology, A dynamic reconfigurable Cache scheme based on branch instruction frequency and a dynamic reconfigurable Cache scheme based on instruction time number are proposed. The dynamic reconfigurable Cache technology is to dynamically adjust the structure of Cache according to the requirements of the program during the running of the program. The energy consumption of idle and unused parts of Cache is closed so that the power consumption of Cache is reduced effectively under the condition of minimum performance loss. The BRDRC algorithm monitors whether the program segment changes according to the branch instruction frequency, and determines the capacity adjustment. In the program segment, the state machine adjusts the correlation degree of Cache according to the dynamic configuration strategy. Then, according to the missing rate of Cache in the new configuration, the optimal structure of the current program segment Cache is determined. Compared with the existing algorithms, the proposed algorithm not only reduces the Cache power consumption more effectively, but also greatly reduces the hardware overhead. The IC-DRC algorithm is improved on the BRDRC algorithm, which monitors the program segment according to the instruction time and determines the capacity adjustment. In the program segment, the state machine prejudges the Cache access according to the average access time. Then the Cache structure of the current program segment is determined according to the results of the pre-judgment. The introduction of the pre-judgment mechanism can not only effectively avoid unnecessary refactoring. At the same time, the average access time is better than the missing rate. The experimental results show that compared with the BRDRC algorithm and the existing algorithm, the IC-DRC algorithm significantly improves the performance loss and further reduces the Cache power consumption.
【學位授予單位】：湖南大學
【學位級別】：碩士
【學位授予年份】：2012
【分類號】：TP332

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