本文關(guān)鍵詞： MTV體系結(jié)構(gòu) 模擬器 多線程 向量　出處：《國(guó)防科學(xué)技術(shù)大學(xué)》2012年碩士論文　論文類型：學(xué)位論文

【摘要】：隨著單核微體系結(jié)構(gòu)的不斷改進(jìn)，程序的指令級(jí)并行性已基本上開(kāi)發(fā)殆盡，目前國(guó)際上微處理器的主要發(fā)展方向是發(fā)掘程序的任務(wù)級(jí)并行性和數(shù)據(jù)級(jí)并行性。本文試圖在傳統(tǒng)的單核體系結(jié)構(gòu)基礎(chǔ)上，深入發(fā)掘任務(wù)級(jí)并行性和數(shù)據(jù)級(jí)并行性，從多個(gè)層面提升微處理器性能。本文提出了面向科學(xué)計(jì)算的眾線程寬向量（Many-Thread wide Vector，MTV）體系結(jié)構(gòu)，能夠同時(shí)開(kāi)發(fā)程序的指令級(jí)并行性、任務(wù)級(jí)并行性和數(shù)據(jù)級(jí)并行性。 本文的主要工作包括兩個(gè)方面，即MTV體系結(jié)構(gòu)建模和MTV體系結(jié)構(gòu)的性能分析。 首先，本文對(duì)MTV體系結(jié)構(gòu)進(jìn)行了功能建模和性能建模，，形成了一款執(zhí)行驅(qū)動(dòng)的MTV體系結(jié)構(gòu)全系統(tǒng)模擬器。功能建模方面，該模擬器建模了MTV體系結(jié)構(gòu)的寄存器、存儲(chǔ)器和指令執(zhí)行引擎，支持引導(dǎo)未經(jīng)修改的操作系統(tǒng)，并且采用了指令譯碼緩沖和地址翻譯緩沖等多種優(yōu)化技術(shù)提升性能。性能模擬方面，建模了一條支持硬件多線程的亂序執(zhí)行流水線，建模了分支預(yù)測(cè)、亂序執(zhí)行、硬件多線程、Cache層次和片上互連網(wǎng)絡(luò)等多種微體系結(jié)構(gòu)部件。MTV模擬器采用模塊化設(shè)計(jì)思想，利用動(dòng)態(tài)鏈接技術(shù)，實(shí)現(xiàn)了模擬器各部件模型的動(dòng)態(tài)加載，使得模擬器具有很高的靈活性。 其次，本文在MTV模擬器內(nèi)實(shí)現(xiàn)了一個(gè)片上存儲(chǔ)系統(tǒng)的Profiling框架，并在此基礎(chǔ)上對(duì)MTV體系結(jié)構(gòu)的存儲(chǔ)系統(tǒng)進(jìn)行了初步研究和性能分析，包括多線程對(duì)訪存延遲的容忍程度和向量存儲(chǔ)對(duì)存儲(chǔ)結(jié)構(gòu)的影響兩個(gè)方面�；趯�(duì)實(shí)驗(yàn)數(shù)據(jù)的分析，提出了一種適合標(biāo)量和向量混合存儲(chǔ)的存儲(chǔ)器改進(jìn)方案，并進(jìn)行了一定的性能分析。
[Abstract]:With the continuous improvement of the single-core microarchitecture, the instruction level parallelism of the program has basically been developed. At present, the main development direction of microprocessor in the world is to explore the task level parallelism and data level parallelism of programs. This paper attempts to explore the task level parallelism and data level parallelism on the basis of the traditional single core architecture. In this paper, we propose a multithread wide vector many-Thread wide VectorMTV architecture for scientific computing, which can simultaneously develop the command level parallelism, task level parallelism and data level parallelism of programs. The main work of this paper includes two aspects: modeling of MTV architecture and performance analysis of MTV architecture. First of all, the function modeling and performance modeling of MTV architecture are carried out, and an executive-driven MTV architecture full-system simulator is formed. In terms of functional modeling, the simulator models the register of MTV architecture. Memory and instruction execution engine, supporting the boot of unmodified operating system, and using a variety of optimization techniques such as instruction decoding buffer and address translation buffer to improve performance. In this paper, we model pipeline, which supports hardware multithreading, model branch prediction, scramble execution, hardware multithreading Cache hierarchy and on-chip interconnection network. MTV simulator adopts modularization design idea. The dynamic link technology is used to realize the dynamic loading of each component model of the simulator, which makes the simulator have high flexibility. Secondly, a Profiling framework of on-chip storage system is implemented in the MTV simulator, and the storage system of MTV architecture is studied and analyzed on this basis. This paper includes two aspects: the tolerance of multithreading to memory access delay and the effect of vector storage on memory structure. Based on the analysis of experimental data, a memory improvement scheme suitable for scalar and vector hybrid storage is proposed. A certain performance analysis was carried out.
【學(xué)位授予單位】：國(guó)防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2012
【分類號(hào)】：TP332

【參考文獻(xiàn)】

相關(guān)期刊論文 前8條

1 王曄;臧斌宇;朱傳琪;;二維SIMD體系結(jié)構(gòu)研究與模擬器實(shí)現(xiàn)[J];計(jì)算機(jī)工程與應(yīng)用;2007年25期

2 路放;安虹;梁博;任建;;OpenSMT:一個(gè)同時(shí)多線程處理器模擬器的設(shè)計(jì)和實(shí)現(xiàn)[J];計(jì)算機(jī)科學(xué);2006年01期

3 錢興隆;臧斌宇;朱傳琪;;一種SIMD優(yōu)化中的向量寄存器部分重用方法[J];計(jì)算機(jī)工程與科學(xué);2007年05期

4 李莉,沈緒榜;LSSIMD陣列微處理器的控制邏輯設(shè)計(jì)[J];計(jì)算機(jī)學(xué)報(bào);2000年05期

5 陳朝陽(yáng),王忠,沈緒榜,桑紅石,趙冰茹,陳小鐵;LS MPP并行圖像處理機(jī)[J];計(jì)算機(jī)學(xué)報(bào);2002年03期

6 李祖松;許先超;胡偉武;唐志敏;;龍芯2號(hào)處理器的同時(shí)多線程設(shè)計(jì)[J];計(jì)算機(jī)學(xué)報(bào);2009年11期

7 佟冬,方濱興,胡銘曾;用非線性存儲(chǔ)方案設(shè)計(jì)SIMD計(jì)算機(jī)的一般方法[J];計(jì)算機(jī)研究與發(fā)展;2000年02期

8 劉坤杰;秦興;嚴(yán)曉浪;李德賢;彭劍英;;EDO-SIMD:內(nèi)嵌數(shù)據(jù)組織的SIMD多媒體擴(kuò)展指令集[J];浙江大學(xué)學(xué)報(bào)(工學(xué)版);2008年04期

相關(guān)博士學(xué)位論文 前1條

1 歐國(guó)東;基于線程的數(shù)據(jù)預(yù)取技術(shù)研究[D];國(guó)防科學(xué)技術(shù)大學(xué);2011年

本文編號(hào)：1545992