發(fā)布時間：2018-02-27 23:19

  本文關(guān)鍵詞： DSP FPGA SOPC 串行通信 Avalon外設(shè) 在線編程　出處：《南京理工大學(xué)》2012年碩士論文　論文類型：學(xué)位論文

【摘要】：隨著通信技術(shù)和嵌入式系統(tǒng)的發(fā)展,嵌入式通信系統(tǒng)廣泛應(yīng)用于工業(yè)、國防、航空航天等領(lǐng)域。因此,嵌入式通信系統(tǒng)的數(shù)據(jù)通信是否可靠,對整個系統(tǒng)的性能顯得至關(guān)重要�；诖四康�,本文基于實際應(yīng)用背景并結(jié)合當(dāng)前SOPC (System On a Programmable Chip,片上可編程系統(tǒng))技術(shù),研究了一種基于SOPC的可重構(gòu)通信測試系統(tǒng)。 本文設(shè)計實現(xiàn)了基于SOPC的可重構(gòu)通信測試系統(tǒng),該系統(tǒng)對RS-485、CAN通信錯誤、設(shè)備通信線路故障提供解決方案。本文以測試系統(tǒng)的實現(xiàn)為主線展開論述,首先從總體上對系統(tǒng)的性能指標(biāo)、功能等方面進行了介紹,然后著重對系統(tǒng)各個部分的功能實現(xiàn)進行了分析及論述。設(shè)計工作大致可分為下位機設(shè)計和上層監(jiān)控系統(tǒng)設(shè)計。 下位機以DSP+FPGA雙處理器的體系結(jié)構(gòu)搭建硬件平臺。其中DSP TMS320F2812主要負責(zé)對四路模擬電壓信號的采集、EPCS4在線編程及與上位機進行RS-232串口通信；FPGA采用Altera公司的CycloneⅡEP2C8Q208I8N,將UART、CAN控制器等以Avalon外設(shè)的形式集成到自定義的NiosⅡ處理器中,以一種全新、靈活的方式,與通信設(shè)備進行RS-485、CAN串行通信。為了能夠保障通信的可靠性及連續(xù)性,在軟硬件設(shè)計中,都采用冗余設(shè)計思想。 上層監(jiān)控系統(tǒng)利用VC++編程語言設(shè)計完成,主要實現(xiàn)與單板系統(tǒng)的通信、對通信測試結(jié)果的分析和顯示功能。 最后,在上層監(jiān)控系統(tǒng)與單板系統(tǒng)之間開展了聯(lián)調(diào)測試工作。測試結(jié)果表明本系統(tǒng)性能達到了設(shè)定的指標(biāo)要求。
[Abstract]:With the development of communication technology and embedded system, embedded communication system is widely used in industry, national defense, aerospace and other fields. It is very important to the performance of the whole system. For this purpose, a reconfigurable communication testing system based on SOPC is studied in this paper, based on the practical application background and the current SOPC system on a Programmable Chip (Programmable system on Chip) technology. A reconfigurable communication test system based on SOPC is designed and implemented in this paper. The system provides a solution for RS-485 can communication error and equipment communication line fault. Firstly, the performance index and function of the system are introduced in general, and then the function realization of each part of the system is analyzed and discussed. The design work can be divided into lower computer design and upper monitor system design. The hardware platform is built by DSP FPGA dual-processor architecture, in which DSP TMS320F2812 is mainly responsible for on-line programming of four analog voltage signals and RS-232 serial port communication with host computer. Cyclone 鈪，

本文編號：1544752