本文關(guān)鍵詞： X-DSP ASU運(yùn)算單元 定點(diǎn)運(yùn)算 浮點(diǎn)運(yùn)算 驗(yàn)證 綜合 優(yōu)化策略　出處：《國防科學(xué)技術(shù)大學(xué)》2013年碩士論文　論文類型：學(xué)位論文

【摘要】：數(shù)字信號(hào)處理器（DSP）是對(duì)信號(hào)和圖像實(shí)現(xiàn)實(shí)時(shí)處理的一類芯片，具有高效率、低功耗和低成本的特點(diǎn)。隨著DSP芯片的飛速發(fā)展，它在通信、軍事、家電等社會(huì)生活的各個(gè)領(lǐng)域得到了廣泛的應(yīng)用，同時(shí)，越來越多的應(yīng)用對(duì)DSP的性能也提出了更高的要求。 X-DSP芯片是一款研制中的32位高性能DSP。該DSP屬于自主正向設(shè)計(jì)，實(shí)現(xiàn)多功能定點(diǎn)和浮點(diǎn)運(yùn)算，擁有極其強(qiáng)大的定點(diǎn)和浮點(diǎn)數(shù)值運(yùn)算能力。它采用超長指令字（VLIW）技術(shù)和單指令流多數(shù)據(jù)流（SIMD）技術(shù)，設(shè)計(jì)目標(biāo)主頻達(dá)到1GHz。加法移位單元ASU（AddShift Unit）是X-DSP中定點(diǎn)和浮點(diǎn)運(yùn)算的主要執(zhí)行部件之一，本文在深入研究其指令功能的基礎(chǔ)之上，設(shè)計(jì)并實(shí)現(xiàn)了該運(yùn)算單元。主要內(nèi)容如下： 一、從ASU運(yùn)算單元的總體設(shè)計(jì)入手，，按照基于標(biāo)準(zhǔn)單元的設(shè)計(jì)流程對(duì)其進(jìn)行了層次化的設(shè)計(jì)，同時(shí)結(jié)合全定制的設(shè)計(jì)方法，對(duì)ASU運(yùn)算單元的移位關(guān)鍵部件進(jìn)行了定制設(shè)計(jì)，達(dá)到了整體設(shè)計(jì)目標(biāo)。 二、深入研究了ASU運(yùn)算單元的結(jié)構(gòu)，合理地劃分了子功能模塊，并采用多種方法和設(shè)計(jì)技巧對(duì)各個(gè)子功能模塊和關(guān)鍵部件進(jìn)行了邏輯設(shè)計(jì)，達(dá)到了時(shí)序的要求。 三、對(duì)編寫好的RTL級(jí)代碼進(jìn)行了模擬功能驗(yàn)證，開發(fā)了ASU運(yùn)算單元的測(cè)試向量，并結(jié)合FPGA的驗(yàn)證方法，對(duì)目標(biāo)設(shè)計(jì)進(jìn)行了補(bǔ)充驗(yàn)證，充分保證了ASU運(yùn)算單元的功能正確性。 四、總結(jié)了ASU運(yùn)算單元在邏輯綜合時(shí)應(yīng)考慮的一些問題，并針對(duì)設(shè)計(jì)的特點(diǎn)和要求，提出了多種優(yōu)化策略對(duì)目標(biāo)設(shè)計(jì)進(jìn)行優(yōu)化，通過對(duì)不同子模塊的多種實(shí)現(xiàn)方案進(jìn)行綜合比較，最后選擇了合適的方法對(duì)ASU運(yùn)算單元進(jìn)行設(shè)計(jì)。 最后，在45nm CMOS工藝下，使用Synopsys公司的綜合工具（DesignCompiler）在worst case條件下對(duì)ASU運(yùn)算單元進(jìn)行邏輯綜合，時(shí)序、面積和功耗方面都獲得了比較令人滿意的結(jié)果：頻率達(dá)到了1GHz的設(shè)計(jì)目標(biāo)，面積為63709.329829平方微米，動(dòng)態(tài)功耗和靜態(tài)功耗分別為10.5928mW和1.6359mW。
[Abstract]:Digital signal processor (DSP) is a kind of chip for real-time processing of signal and image. It has the characteristics of high efficiency, low power consumption and low cost. With the rapid development of DSP chip, it is in communication and military. Home appliances and other fields of social life have been widely used, at the same time, more and more applications have put forward higher requirements for the performance of DSP. X-DSP chip is a 32-bit high-performance DSP, which belongs to the autonomous forward design and realizes multi-function fixed-point and floating-point operation. It has extremely powerful fixed-point and floating-point value computing capability. It adopts VLIW (very long instruction word) technology and SIMD technology of single instruction stream and multiple data streams. The main frequency of the design is 1 GHz. The additive shift unit (ASU(AddShift) is one of the main execution components of fixed point and floating-point operation in X-DSP. Based on the in-depth study of its instruction function, this paper designs and implements the operation unit. The main contents are as follows: First, starting from the overall design of the ASU operation unit, according to the design process based on the standard unit, the hierarchical design is carried out, and the fully customized design method is combined at the same time. The shift key components of ASU operation unit are customized, and the overall design goal is achieved. Secondly, the structure of ASU operation unit is deeply studied, the sub-function module is divided reasonably, and various sub-function modules and key components are logically designed by various methods and design techniques. Meet the requirements of timing. Thirdly, the simulation function of the RTL code is verified, the test vector of the ASU operation unit is developed, and the target design is supplemented with the verification method of FPGA. The functional correctness of ASU operation unit is fully guaranteed. Fourthly, some problems that should be considered in logic synthesis of ASU operation unit are summarized. According to the characteristics and requirements of the design, various optimization strategies are proposed to optimize the target design. Through the comprehensive comparison of various implementation schemes of different sub-modules, a suitable method is selected to design the ASU operation unit. Finally, in 45nm CMOS process. Using the synthetic tool of Synopsys Company, Design Compiler, under the condition of worst case, the logic synthesis and timing of ASU operation unit are carried out. The results of area and power consumption are satisfactory: the frequency has reached the design target of 1GHz, the area is 63709.329829 square micron. The dynamic and static power consumption are 10.5928mW and 1.6359mW, respectively.
【學(xué)位授予單位】：國防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2013
【分類號(hào)】：TP332

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相關(guān)期刊論文 前1條

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