發(fā)布時間：2018-01-21 14:30

  本文關鍵詞： 抗輻射加固 靜態(tài)隨機存儲器 單粒子翻轉 單粒子閂鎖 糾檢錯碼　出處：《西安電子科技大學》2015年碩士論文　論文類型：學位論文

【摘要】：隨著集成電路的高速發(fā)展,存儲器占據越來越重要的地位。其中,靜態(tài)隨機存儲器(SRAM)因其速度快、功耗低已被廣泛應用于各種高速存儲器中。同時,SRAM在各類航天器件的電路系統(tǒng)中也有著更為廣泛的應用。在空間輻射環(huán)境中,SRAM會嚴重受到單粒子翻轉效應、單粒子閂鎖效應、總劑量效應等的影響。因此,航天用到的SRAM不僅要保證其本身的特性,還應該具備更好的抗輻射性能。本課題源于航天某項目,對其中所需SRAM,進行了抗輻射加固性能的設計。SRAM中最重要的部分是存儲單元,首先對標準6管SRAM存儲單元的性能和多種具有抗輻射性能的存儲單元電路設計進行了分析,設計出能夠符合項目指標要求,且具有抗輻射性能的SRAM存儲單元。以存儲單元為核心,設計具有一定抗輻射性能的外圍電路,構成完整的SRAM設計。在電路設計的基礎上實現物理版圖。著重版圖的抗輻射加固方法,以提高抗單粒子性能。然后使用star-RCXT提取版圖的^/寄生參數的網表,和使用Hspice與Spectre兩個仿真軟件進行仿真驗證,完成對SRAM的功能和性能的檢查驗證,以此來滿足設計指標。本文的重點在于兩個方面。一方面是著重在版圖上對SRAM進行抗輻射加固的設計。在版圖中,(1)通過增加阱或襯底接觸的保護環(huán)、保護^/;(2)增加阱或襯底接觸上的通孔(CT)孔的數量;(3)拉大N型金屬氧化物半導體(NMOS)和P型金屬氧化物半導體(PMOS)的距離等多種加固措施加固措施,使SRAM具有很好的抗單粒子效應(SEE)的能力。另一方面是設計糾檢錯碼(EDAC)電路,采用漢明碼的編碼方式,具有糾一檢二的工作方式,能夠具有更好的抗單粒子翻轉(SEU)效應的能力。而EDAC的版圖是由具有抗輻射性能的單元庫的基本邏輯單元拼接構成。本項目是基于中芯國際(SMIC)的130nm工藝,使用candance工具進行的設計。通過與某商用SRAM相比,較商用的讀寫時間慢2秒鐘左右。而在抗單粒子效應方面,通過單粒子仿真軟件,模擬金(Au)粒子入射存儲單元,得到的結果顯示無閂鎖效應發(fā)生;另外又采用EDAC電路,保證不會出現由單粒子效應引起的一位翻轉錯誤,具有良好的抗單粒子效應的性能。
[Abstract]:With the rapid development of integrated circuits, memory occupies a more and more important position. Among them, static random access memory (SRAM) has been widely used in all kinds of high-speed memory because of its high speed and low power consumption. SRAM is also widely used in the circuit system of various spaceflight devices. In the environment of space radiation, SRAM will be seriously affected by single particle flip effect and single particle latch effect. Therefore, the SRAM used in aerospace should not only guarantee its own characteristics, but also have better radiation resistance. The most important part of SRAM is memory cell. Firstly, the performance of the standard 6-tube SRAM memory cell and the design of a variety of memory cell circuits with anti-radiation performance are analyzed, and the design can meet the requirements of the project. The SRAM memory cell with anti-radiation performance is designed with the memory cell as the core, and the peripheral circuit with certain anti-radiation performance is designed. Form a complete SRAM design. Based on the circuit design to achieve physical layout, focusing on the layout of anti-radiation reinforcement method. In order to improve the anti-single particle performance, star-RCXT is used to extract the net table of ^ / parasitic parameters of the layout, and two simulation software, Hspice and Spectre, are used for simulation verification. Check and verify the function and performance of SRAM. This paper focuses on two aspects. On the one hand, it focuses on the design of anti-radiation reinforcement of SRAM on the layout. (1) protect ^ / R by increasing the trap or substrate contact protection ring; (2) increasing the number of CTs on a well or substrate contact; Strengthening measures such as enlarging the distance between N type metal oxide semiconductor (NMOS) and P type metal oxide semiconductor (PMOS). The SRAM has the ability to resist single particle effect (SEE). On the other hand, it designs the error-correcting code (EDAC) circuit, which adopts the hamming code coding method and has the operation mode of correcting one and checking two. The layout of EDAC is composed of basic logical unit splicing of unit library with radiation resistance. This project is based on SMIC (SMIC). The 130nm process of SMICs. Design using candance tools. Compared with a commercial SRAM, the reading and writing time is about 2 seconds slower than that of commercial SRAM. In the aspect of anti-single particle effect, the software of single particle simulation is used. The simulated au) particles incident into the memory cell and the results show that there is no latch effect. In addition, EDAC circuit is used to guarantee that there will not be a bit flip error caused by single particle effect, so it has good performance against single particle effect.
【學位授予單位】：西安電子科技大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TP333

【參考文獻】

相關期刊論文 前1條

1 衛(wèi)寧;王劍峰;杜婕;周聰莉;郭旗;文林;;抗輻射加固封裝國產存儲器的電子輻照試驗[J];信息與電子工程;2010年01期

，

本文編號：1451733