本文選題：軟錯誤屏蔽　切入點：單粒子瞬態(tài)　出處：《合肥工業(yè)大學》2017年碩士論文

【摘要】：隨著數(shù)字集成電路的工藝尺寸不斷縮小,電源電壓持續(xù)降低,電路的節(jié)點電容不斷減小,電路節(jié)點翻轉(zhuǎn)所需要的臨界電荷相應減小,單粒子翻轉(zhuǎn)和單粒子瞬態(tài)變得愈發(fā)嚴重。同時由于時鐘頻率的不斷上升,組合邏輯中發(fā)生單粒子瞬態(tài)的概率也在不斷上升。所以,設計抗單粒子瞬態(tài)和單粒子翻轉(zhuǎn)的集成電路成為急需解決的問題。本文針對納米工藝集成電路的軟錯誤問題,在研究現(xiàn)有加固鎖存器設計的基礎上,提出了有效的抗輻射加固鎖存器設計方案,本文的主要工作如下:介紹了國內(nèi)外集成電路抗輻射加固的研究現(xiàn)狀,以及輻射環(huán)境的背景知識和輻射效應的分類。闡明了集成電路軟錯誤的基本概念,詳細分析了單粒子效應的分類、機理及其故障模型。重點分析了單粒子瞬態(tài)和單粒子翻轉(zhuǎn)引起集成電路發(fā)生軟錯誤的原理以及瞬態(tài)故障的建模分析方法。針對單粒子瞬態(tài)和單粒子翻轉(zhuǎn)對鎖存器的影響,總結(jié)了國內(nèi)外學者提出的鎖存器加固方案,并分析了這些加固方案的設計原理,對其優(yōu)缺點進行了比較�？箚瘟Ｗ铀矐B(tài)的設計方法通常是在組合電路后端使用過濾電路�？箚瘟Ｗ臃D(zhuǎn)的設計方法有三模冗余、基于C單元的冗余反饋回路和檢錯糾錯等方法。同時抗單粒子瞬態(tài)和單粒子翻轉(zhuǎn)的設計方法有時間冗余與硬件冗余的結(jié)合,以及包含延遲單元的鎖存器。目前已有的加固設計主要集中在防護單粒子翻轉(zhuǎn),沒有考慮單粒子瞬態(tài)對電路的影響。在分析已有加固鎖存器的基礎上,提出了一種基于PTM 45nm工藝模型的抗輻射加固鎖存器設計。由一個施密特觸發(fā)器、三個傳輸門、三個反相器和三個C單元組成。利用施密特觸發(fā)器和反相器構(gòu)建時間冗余,屏蔽從上游組合邏輯傳來的單粒子瞬態(tài);三個交叉互鎖的C單元中任意一個的輸出由其他兩個的輸出決定,當內(nèi)部節(jié)點受到高能粒子轟擊發(fā)生邏輯翻轉(zhuǎn),通過C單元的軟錯誤屏蔽能力來實現(xiàn)內(nèi)部節(jié)點的自恢復,從而達到容忍單粒子翻轉(zhuǎn)的目的。HSPICE的仿真結(jié)果表明,與其他的加固設計相比本文的加固設計的面積、延遲、功耗和PDP分別平均下降了 15.84%、10.31%、46.71 %和 37.72%。
[Abstract]:With the continuous reduction of the process size of the digital integrated circuit, the power supply voltage continues to decrease, the node capacitance of the circuit continues to decrease, the critical charge required for the circuit node flipping is reduced accordingly, and the single-particle flip and single-particle transient become more and more serious.At the same time, the probability of single particle transient in combinational logic is increasing because of the rising clock frequency.Therefore, the design of single-particle transient and single-particle flip-resistant integrated circuits has become an urgent problem.In this paper, aiming at the problem of soft errors in nanoscale integrated circuits, an effective design scheme of anti-radiation strengthened latch is proposed on the basis of studying the existing design of strengthened latch.The main work of this paper is as follows: this paper introduces the research status of integrated circuit radiation reinforcement at home and abroad, as well as background knowledge of radiation environment and classification of radiation effect.The basic concept of integrated circuit soft error is expounded, and the classification, mechanism and fault model of single particle effect are analyzed in detail.The principle of soft error caused by single particle transient and single particle flip and the modeling and analysis method of transient fault are analyzed.Aiming at the effect of single particle transient and single particle flip on latch, the reinforcement schemes of latch proposed by domestic and foreign scholars are summarized, and the design principles of these reinforcement schemes are analyzed, and their advantages and disadvantages are compared.Anti-single-particle transient design usually uses filter circuits at the back end of combinational circuits.The design method of anti-single particle flip has three modes redundancy, redundant feedback loop based on C element and error detection and correction methods.The design methods of resisting single particle transient and single particle flipping include the combination of time redundancy and hardware redundancy, as well as latch with delay unit.At present, the existing reinforcement design mainly focuses on the protection of single particle inversion, without considering the effect of single particle transient on the circuit.Based on the analysis of existing strengthened latch, a design of anti-radiation reinforcement latch based on PTM 45nm process model is proposed.It consists of a Schmidt trigger, three transmission gates, three inverters and three C units.Schmitt flip-flop and inverter are used to construct time redundancy to shield single particle transient from upstream combinational logic, and the output of any one of the three interlocking C cells is determined by the output of the other two.When the internal node is bombarded by high energy particles, the logic flip occurs, and the self-recovery of the internal node is realized by the soft error shielding ability of the C unit, and the simulation results show that the single particle flip can be tolerated.Compared with other reinforcement designs, the area, delay, power consumption and PDP of the reinforcement design in this paper are reduced by 15.84% and 37.72%, respectively.
【學位授予單位】：合肥工業(yè)大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TN402

【參考文獻】

相關期刊論文 前8條

1 黃正峰;錢棟良;梁華國;易茂祥;歐陽一鳴;閆愛斌;;65nm工藝下單粒子加固鎖存器設計[J];計算機輔助設計與圖形學學報;2016年08期

2 ;國家集成電路產(chǎn)業(yè)發(fā)展推進綱要[J];中國集成電路;2014年07期

3 黃正峰;陳凡;蔣翠云;梁華國;;基于時序優(yōu)先的電路容錯混合加固方案[J];電子與信息學報;2014年01期

4 張現(xiàn)亮;朱敏波;李琴;;空間輻照機理與防護技術(shù)研究[J];空間電子技術(shù);2007年03期

5 華更新,王國良,郭樹玲;星載計算機抗輻射加固技術(shù)[J];航天控制;2003年01期

6 王麗君;空間電子學的單粒子效應[J];空間電子技術(shù);1998年04期

7 王長河;單粒子效應對衛(wèi)星空間運行可靠性影響[J];半導體情報;1998年01期

8 閔應驊;容錯計算二十五年[J];計算機學報;1995年12期

相關博士學位論文 前1條

1 劉必慰;集成電路單粒子效應建模與加固方法研究[D];國防科學技術(shù)大學;2009年

，

本文編號：1714618