本文選題：三維測試外殼　切入點：硅通孔　出處：《合肥工業(yè)大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

【摘要】：隨著集成電路工藝技術(shù)的發(fā)展,品體管尺寸逐漸減小,互連線的延遲超過了邏輯門的延遲,成為提升系統(tǒng)性能的主要瓶頸,三維集成電路(Three-Dimension Integrated Circuit,3D IC)能顯著減低互連線延遲和系統(tǒng)功耗,成為一種有效解決互連線問題的方法。三維片上系統(tǒng)(Three-Dimension System-on-a-chip,3D SoC)結(jié)合了3D IC和片上系統(tǒng)(System-on-a-chip, SoC)的優(yōu)點,逐漸成為集成電路領(lǐng)域的主流。3D SoC有粗[粒度劃分和細(xì)粒度劃分兩種劃分方式。在粗粒度劃分中,3D SoC上的嵌入式芯核是按照二維的方法設(shè)計；在細(xì)粒度劃分中,每個嵌入式芯核包含多層電路。細(xì)粒度劃分的3D SoC能有效的減少時間延遲并提升性能,但給三維測試外殼的設(shè)計帶來了很大困難。對測試外殼的設(shè)計直接決定了SoC的測試時間。本論文主要目的就是設(shè)計測試外殼的優(yōu)化方法來減少3D SoC的測試時間,主要創(chuàng)新點和貢獻(xiàn)如下：1.提出在TSVs與測試襯墊數(shù)量限制下,總測試時間和硬件開銷協(xié)同優(yōu)化的算法本文提出了在硅通孔(Through-silicon-vias, TSVs)數(shù)量和測試襯墊(test pad)數(shù)量限制下,減少3D SoC綁定前后總測試時間的3DTW0 (3D test wrapper optimization)算法,該算法將每條綁定前的測試外殼掃描鏈作為一個整體,將其分配到各電路層和綁定后的測試外殼掃描鏈,以減少總的測試時間和硬件開銷。同時平衡綁定前和綁定后測試外殼掃描鏈,而不是分開優(yōu)化綁定前和綁定后的測試外殼,這是本方法的一個特色。在ITC'02基準(zhǔn)電路上的實驗結(jié)果表明,與文獻(xiàn)[24]的經(jīng)典算法相比,本方法極大的降低了SoC的總測試時間,并且所用的硬件開銷也不多。2.提出了在TSVs數(shù)量限制下的三維測試外殼優(yōu)化算法本文基于BFD(Best Fit Decreasing)和遺傳算法(Genetic Algorithm, GA),提出BGA(BFD and GA)方法在TSVs數(shù)量的約束下優(yōu)化三維測試外殼,以減少三維嵌入式芯核總的測試時間。BGA方法首先利用BFD算法來平衡綁定前各條測試外殼掃描鏈,以減少綁定前測試時間,然后在綁定前測試外殼掃描鏈優(yōu)化好的基礎(chǔ)上,利用遺傳算法在TSVs數(shù)量的約束下來平衡綁定后的各條測試外殼掃描鏈,以減少綁定后的測試時間。并且BGA方法對綁定后測試外殼的優(yōu)化是在綁定前測試外殼優(yōu)化的基礎(chǔ)上,減少了掃描鏈重構(gòu)所需的硬件開銷。在ITC'02基準(zhǔn)電路上的實驗結(jié)果可知, BGA方法使SoC的測試總時間稍微有所增加,但大幅度減少了硬件開銷。3.提出了減少3D SoC總測試時間的優(yōu)化算法本文將減少3D SoC測試總時間為第一優(yōu)化目的,利用BFD和AL (Allocate Layer)算法將掃描元素分配到測試外殼掃描鏈和層上。此方法首先將三維嵌入式芯核的所有掃描元素投影到一個平面上,用BFD算法將掃描元素分配到各條測試外殼掃描鏈,以減少綁定后的測試時間。再用提出的AL算法將掃描元素分配到各層電路中,使得綁定前各條測試外殼掃描鏈的長度也能夠平衡,以減少綁定前的測試時間和所需TSVs的數(shù)量,并且AL算法能夠使得各層電路所含的掃描元素總長度盡可能的相等。在ITC'02基準(zhǔn)電路上的實驗結(jié)果表明,本文提出的方法減少了測試總時間,并且使三維嵌入式芯核各層電路所含掃描元素的總長度更加均勻。
[Abstract]:With the development of integrated circuit technology, transistor size decreases, the interconnect delay exceeds the delay of logic gates, has become a major bottleneck to improve the performance of the system, the three-dimensional integrated circuit (Three-Dimension Integrated Circuit, 3D IC) can significantly reduce the interconnect delay and power consumption of the system, a method of a effective solution to each other line. The 3D system on chip (Three-Dimension System-on-a-chip, 3D SoC) combined with IC and 3D system on chip (System-on-a-chip, SoC) has gradually become a "coarse granularity and fine grained division two division of integrated circuit in the field of mainstream.3D SoC. In coarse granularity, embedded core 3D SoC the design is in accordance with the two methods; in the fine-grained classification, each embedded core contains a multilayer circuit. Fine grained division 3D SoC can effectively reduce the time delay and improve the performance, but It is difficult to design a three-dimensional test case. The test case design directly determines the test time of SoC optimization method. The main purpose of this paper is to design test case to reduce the test time of 3D SoC, the main innovations and contributions are as follows: 1. in TSVs is put forward and a testing pad under a number of constraints, the total test time the hardware overhead and collaborative optimization algorithm is presented in this paper through silicon vias (Through-silicon-vias, TSVs) and the number of test pads (test pad) the number of constraints, reduce the total test time before and after 3D SoC binding 3DTW0 (3D test wrapper optimization) algorithm, the algorithm will scan chain test case before each binding as a whole and distribute it to the wrapper scan chain circuit layer and binding, to reduce the test time and hardware overhead. At the same time the total balance before and after binding, binding test shell scan chain Instead, separate the test before and after optimization of shell binding binding, which is a feature of the method. The experimental results on ITC'02 benchmark circuits show that compared with the classical algorithm of [24], this method greatly reduces the total test time of SoC, and the hardware overhead is not much.2. based on the TSVs limit on the number of the three-dimensional test shell optimization algorithm based on BFD (Best Fit Decreasing) and genetic algorithm (Genetic Algorithm GA), BGA (BFD and GA) proposed method of 3D test shell optimization in the number of TSVs constraints, to reduce the three-dimensional embedded core test of general.BGA method first time using BFD algorithm to balance the test case before binding the scan chain to reduce test time and test before binding, a good case based scan chain optimization in the bound before, using the genetic algorithm in the number of TSVs about balance beam tied down The scan chain test shell after calibration, in order to reduce the test time bound. And the BGA method to optimize the binding test of the housing is based on Optimization of the binding test shell, reducing the scan chain reconfiguration required hardware overhead. Experimental results on ITC'02 benchmark circuits show that the BGA method to test the total the time of SoC increased slightly, but greatly reduces the hardware overhead of.3. is proposed to reduce the 3D SoC optimization algorithm for the total test time will be reduced by 3D SoC for the first time the total test optimization purposes, the use of BFD and AL (Allocate Layer) algorithm will scan the elements assigned to the test scan chain and shell layer. This method first all the elements of 3D embedded core scanning projection onto a plane, using the BFD algorithm will scan the elements assigned to each test case scan chain, in order to reduce the test time. Then put forward after binding AL The algorithm will scan the elements assigned to each layer in the circuit, so that the test case bound before the scan chain length to balance, to reduce the test time bound before and the required number of TSVs, the total length of the scan element and the AL algorithm can make the circuit layer contains as much as possible in the ITC'02 benchmark circuits are equal. The experimental results show that the proposed method reduces the total test time, and the total length of the three-dimensional embedded core circuit of each layer contains scanning elements more uniform.

【學(xué)位授予單位】：合肥工業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN407

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