本文選題：正電子斷層發(fā)射掃描 + 可編程門陣列　； 參考：《中國科學院研究生院（長春光學精密機械與物理研究所）》2012年碩士論文

【摘要】：正電子發(fā)射斷層掃描(PET-Positron Emission Tomography)是當今最先進的核醫(yī)學成像技術,屬于功能成像技術。它利用放射性的示蹤劑在分子水平上動態(tài)反映人體內各個器官的的代謝水平和生化反應。將飛行時間(TOF)技術應用于PET是一次偉大的技術革新,TOF技術可以將正電子符合湮滅的位置精確定位,減少重建該事件所涉及到的體素數量,局部的信息濃度高,使得定量更加精確、注射劑量更低、成像更快、臨床圖像的分辨率更高。 要想實現對正電子湮滅的精確定位,TOF PET系統(tǒng)必須具有很高的時間分辨率。將FPGA引入到TOF PET時間測量電路和符合判選電路,使設計的電路具有結構簡單、運算量少、體積小等優(yōu)點,為模塊化的TOF PET系統(tǒng)提供了可擴展性和再編程的靈活性。同時使電路獲得非常高的處理速度,可滿足TOF PET對時間分辨率的要求。 本文以~l00ps的時間分辨率為目標,探討TOF PET的時間數字轉換器(TDC)和符合判選電路的設計實現和軟件仿真。從系統(tǒng)的開發(fā)設計環(huán)境出發(fā),介紹了FPGA的基本結構、開發(fā)環(huán)境和開發(fā)語言,討論了TDC的實現技術,并進行了比較與分析,給出了本文所用技術的總體設計,之后進行了具體模塊的設計與實現,獲得了~l00ps的時間分辨率。在符合判選電路部分,基于一種模塊化、低死時間快速符合系統(tǒng)的設計思路,比較了與邏輯符合方法和時間標記排序方法在時間分辨率和系統(tǒng)復雜度等方面的差別,提出了一種分級符合判選方法,使電路在使用很短時間標記的情況下得到了較好的時間分辨率(~l00ps),簡化了系統(tǒng)復雜性。實驗結果表明,這種基于FPGA的TDC電路和符合判選電路可以用較低的代價實現TOF PET符合判選。
[Abstract]:Positron Emission tomography (PET-Positron Emission tomography) is the most advanced nuclear medical imaging technology, which belongs to functional imaging technology.It uses radioactive tracer to dynamically reflect the metabolic level and biochemical reaction of various organs in the human body at the molecular level.The application of time-of-flight (TOF) technology to PET is a great technological innovation. It can accurately locate positron in the position of annihilation, reduce the number of voxels involved in the reconstruction of the event, and have a high local information concentration.It makes the quantification more accurate, the injection dose lower, the imaging faster, and the resolution of clinical images higher.In order to locate positron annihilation accurately, the TOF PET system must have high time resolution.This paper introduces FPGA into TOF PET time measurement circuit and coincidence selection circuit, which makes the designed circuit have the advantages of simple structure, less computation and small volume. It provides extensibility and reprogramming flexibility for the modular TOF PET system.At the same time, the circuit can achieve a very high processing speed, which can meet the time resolution requirements of TOF PET.Aiming at the time resolution of 100ps, this paper discusses the design and implementation of TOF PET time-digital converter and coincidence circuit and its software simulation.This paper introduces the basic structure, development environment and development language of FPGA, discusses the realization technology of TDC, compares and analyzes the technology used in this paper, and gives the overall design of the technology used in this paper.Then the specific module is designed and implemented, and the time resolution of 100 PS is obtained.In the part of coincidence selection circuit, based on a kind of modularization, low dead time fast coincidence system design idea, the difference of time resolution and system complexity between logic coincidence method and time label sorting method is compared.In this paper, a hierarchical coincidence selection method is proposed, which can get a better time resolution and simplify the system complexity under the condition that the circuit is marked in a very short time.The experimental results show that the TDC circuit based on FPGA and the coincidence selection circuit can realize TOF PET coincidence selection at a lower cost.
【學位授予單位】：中國科學院研究生院（長春光學精密機械與物理研究所）
【學位級別】：碩士
【學位授予年份】：2012
【分類號】：R814.42

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本文編號：1755842