本文選題：紅外焦平面探測器芯片 + 微測輻射熱計��； 參考：《電子科技大學》2016年博士論文

【摘要】：非制冷紅外探測器已廣泛地應用于軍事、邊防、消防、工業(yè)檢測、交通等各個領域,人們對于探測器的性能要求也越來越高;為滿足此要求,開展高性能探測器芯片研究應運而生。高性能意味著具有更高信噪比、更高效率,非理想效應的自適應補償功能;同時還應滿足大陣列、輕質量等需求。本論文以完成高性能非制冷紅外探測器芯片一體化設計為目標,研究了一體化設計高性能系統(tǒng)芯片所需的主要關鍵技術。所涉及到的關鍵技術包括:探測器像元建模技術、探測器溫度補償技術、探測器芯片片上ADC技術、探測器芯片非均勻性校正技術、探測器芯片數(shù)字控制技術。論文的主要研究內(nèi)容綜述如下:1、研究了微測輻射熱計型探測器像元電學設計平臺兼容的一體化設計模型。通過數(shù)學推導和參數(shù)仿真,提出了涵蓋器件光-熱-電多物理場特性的線性模型,其可供電學設計平臺使用,以輔助探測器系統(tǒng)一體化設計。該模型與經(jīng)典模型在探測器溫度變化40K時偏差小于5%,具有良好的精度。2、研究了探測器的溫度補償技術,包含自熱效應補償和襯底溫度補償。針對自熱效應提出使用片上電流DAC或片上電阻DAC的方式進行補償。針對襯底溫度導致的非理想效應提出引入補償盲像元的方案用于補償襯底溫度的影響。對于電壓偏置型紅外讀出電路,以采樣運放跨阻的形式引入補償盲像元;對于電流偏置型紅外讀出電路,以積分器積分電阻的形式的引入補償盲像元。利用像元一體化設計模型仿真優(yōu)化設計。經(jīng)樣片測試后在溫度變化為80K時,采用所提溫度補償技術的探測器的輸出變化率約為20%,其響應率變化率約為40%。3、研究了探測器的片上ADC,包括芯片級ADC和列級ADC。首先由使用像元一體化設計模型的讀出電路仿真結果提出片上ADC的性能需求,然后分別研究芯片級ADC和列級ADC。在芯片級ADC方面,以Pipeline ADC為代表展開研究。首先基于Matlab設計并開發(fā)了一套Pipeline ADC功耗優(yōu)化結構軟件,并由該軟件確定了兩種低功耗Pipeline ADC結構。然后提出了一種基于擾動注入(Dither)和動態(tài)元件匹配(Dynamic Element Match,DEM)的數(shù)字后臺算法,以及一種準實時校準的數(shù)字前臺校準方案,該方案可同時實現(xiàn)連續(xù)性校準和增益校準,并將它們分別應用到所提低功耗結構中。由實物樣品測試知,使用數(shù)字后臺算法的Pipeline ADC功耗為299.93mW,DNL為+0.84LSB/-0.94LSB,INL為+0.99LSB/-1.19LSB;而使用數(shù)字前臺算法的Pipeline ADC功耗為280.96mW,DNL為+0.86LSB/-0.75LSB,INL為+1.53LSB/-1.41LSB。在列級ADC方面,以Single Slope ADC為代表展開研究。為了提高Single Slope ADC的轉換速率,本文提出了半周期計數(shù)法、兩步比較法以及行劃分法三種方案;為加強Single Slope ADC信號在探測器芯片上遠距離傳輸時的準確性,提出了電流傳輸方案,避免信號誤碼。通過將補償盲像元引入ADC參考電壓的產(chǎn)生電路,獲得了具有溫度補償功能的Single Slope ADC,該結構可稱為數(shù)字溫度補償結構。通過樣品測試,單個該Single Slope ADC實際21.86mW,估算其應用于1280×1024陣列時的總功耗為290.19mW,DNL為+0.72LSB/-0.71LSB,INL為+1.18LSB/-1.09LSB。當襯底溫度變化80K時,輸出數(shù)字碼658個數(shù)字碼,占數(shù)字動態(tài)范圍的16.1%,響應率變化率為40.6%。4、研究了探測器的非均勻校正方案,針對本論文重點研究的三種讀出電路結構分別提出了非均勻性校正方案以及流程。對于電壓偏置結構、電流偏置結構,本論文提出以片上電壓DAC調節(jié)它們的跨阻運放參考電壓,從而實現(xiàn)一點溫度補償。針對該方法設計了一種精度和范圍可調的片上電壓DAC,該DAC具有4種電壓調節(jié)范圍。由樣片測試,電壓偏置結構的FNP可降低為11.8mV,電流偏置結構的FNP被降低到10.4mV。對于數(shù)字溫度補償結構,本論文提出使用兩個片上電流DAC調節(jié)其偏置電流,從而實現(xiàn)兩點溫度補償。由樣片測試,溫度補償ADC結構的FNP為127.3mV。5、在數(shù)字控制技術方面,研究了陣列掃描方式、幀信號和逐點校正信號的輸入方案以及讀出結果的輸出方案。將電壓偏置結構+Single Slope ADC的ROIC在640×512的陣列下設計制作了大陣列探測器芯片,性能測試結果為平均響應率為8.83codes/K,約為7.33mV/K;RMS噪聲為325.3μV,FPN噪聲為12.1mV,NETD為62.33mK。
[Abstract]:Uncooled infrared detectors have been widely used in various fields such as military, border defense, fire protection, industrial detection and transportation, and the performance requirements of detectors are becoming higher and higher. In order to meet this requirement, high performance detector chip research has been developed. High performance means that it has higher signal-to-noise ratio, more efficient and non ideal effect. In order to complete the design of high performance uncooled infrared detector chip integrated design, the main key technologies needed for integrated design of high performance system chip are studied in this paper. The key technologies involved include: detector pixel modeling technology, detector temperature supplement The compensation technology, the ADC technology on the chip chip, the non uniformity correction technology of the detector chip and the digital control technology of the detector chip are summarized as follows: 1, the integrated design model of the compatible design platform of the micrometer radiation thermeter type detector is studied. The culvert is put forward by mathematical deduction and parameter simulation. A linear model of the characteristics of the multi physical field of light and thermal electric field, which can be used to assist the integrated design of the detector system. The model and the classic model have a deviation of less than 5% and a good precision.2 when the temperature change of the detector is 40K. The temperature compensation technique of the detector is studied, including the self thermal effect compensation and the substrate temperature. To compensate for the self heat effect, the use of the on-chip current DAC or the on-chip resistance DAC is proposed. The compensation blind pixel scheme is introduced to compensate the influence of the substrate temperature for the non ideal effect caused by the substrate temperature. For the current biased infrared readout circuit, the compensation blind pixel is introduced in the form of integrator integral resistance. The design model of the pixel integration is used to simulate the optimization design. When the temperature change is 80K, the output change rate of the detector using the proposed temperature compensation technique is about 20%, and the response rate is about 40%.3. The on-chip ADC of the detector, including chip level ADC and column level ADC., is first proposed by the read-out circuit simulation results using the pixel integrated design model, and then the chip level ADC and the column level ADC. are studied respectively in the chip level ADC, and Pipeline ADC is considered as the representative. First, the design and development of the Pipeline ADC are designed and developed on Matlab. A set of Pipeline ADC power optimization structure software is used to determine two kinds of low power Pipeline ADC structures. Then a digital background algorithm based on disturbance injection (Dither) and dynamic component matching (Dynamic Element Match, DEM) is proposed, and a quasi real-time calibration scheme of digital front desk is proposed. The scheme can be implemented simultaneously. Continuous calibration and gain calibration are applied to the proposed low power structure. The Pipeline ADC power consumption of the digital background algorithm is 299.93mW, the DNL is +0.84LSB/-0.94LSB, and the INL is +0.99LSB/-1.19LSB, while the Pipeline ADC power consumption of the digital front algorithm is 280.96mW and DNL is +0.86LSB/-0.75LSB. In order to improve the conversion rate of Single Slope ADC, L is the representative of +1.53LSB/-1.41LSB. in the column level ADC. In order to improve the conversion rate of Single Slope ADC, this paper proposes a semi periodic counting method, two step comparison method and three schemes of line division, and the accuracy of enhancing the long distance transmission of Single Slope ADC signal on the probe chip. The current transmission scheme avoids the signal error code. By introducing the compensation blind pixel into the ADC reference voltage generating circuit, the Single Slope ADC with the temperature compensation function is obtained. The structure can be called the digital temperature compensation structure. The total work of the 1280 * 1024 array is estimated by the sample test and the actual 21.86mW of the single Single Slope ADC. The consumption is 290.19mW, DNL is +0.72LSB/-0.71LSB, INL is +1.18LSB/-1.09LSB. when the substrate temperature changes 80K, the output digital code is 658 digital codes, which accounts for 16.1% of the digital dynamic range and the response rate change rate is 40.6%.4. The non uniform correction scheme of the detector is studied. The non uniformity of the three readout circuit structures which are mainly studied in this paper are put forward respectively. The uniformity correction scheme and process. For voltage bias structure and current bias structure, this paper proposes to adjust their cross resistance amplifier reference voltage by DAC on chip voltage to achieve a point of temperature compensation. In this method, a precision and range adjustable voltage DAC is designed for this method. The DAC has 4 range of voltage regulation. The voltage bias structure of the FNP can be reduced to 11.8mV, the FNP of the current bias structure is reduced to the 10.4mV. for digital temperature compensation structure. This paper proposes to use two on-chip current DAC to adjust its bias current to achieve two point temperature compensation. The input scheme of the array scanning, the frame signal and the point by point correction signal and the output scheme of the readout result are studied. A large array detector chip is designed and produced by the voltage biased structure of +Single Slope ADC under 640 x 512 array. The performance test result is that the average response rate is 8.83codes/K, about 7.33mV/K, and the RMS noise is 325.3. V, FPN noise is 12.1mV, NETD is 62.33mK.
【學位授予單位】：電子科技大學
【學位級別】：博士
【學位授予年份】：2016
【分類號】：TN215

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本文編號：2027023