本文關(guān)鍵詞： 工藝偏差 片上檢測 電容陣列測量 時域放大器 時序參數(shù)測量 物理不可克隆散列函數(shù)　出處：《浙江大學(xué)》2016年博士論文　論文類型：學(xué)位論文

【摘要】：隨著半導(dǎo)體工業(yè)的發(fā)展,工藝的特征尺寸不斷縮小,芯片的集成度不斷提高,集成電路設(shè)計和制造的復(fù)雜度也不斷增大。當器件的特征尺寸進入納米尺度后,工藝偏差對器件性能帶來很大影響,嚴重制約了集成電路的性能、功耗和成品率等。工藝偏差的檢測技術(shù)是半導(dǎo)體工藝領(lǐng)域的一個研究熱點,它依賴于參數(shù)測量技術(shù)。靜態(tài)參數(shù)和時序參數(shù)是表征工藝偏差的兩個要素。通過片上參數(shù)的提取,可以分析芯片內(nèi)部工藝偏差的分布、建立相關(guān)模型、修改完善工藝步驟,從而降低工藝偏差,加快新工藝的開發(fā)進度。工藝偏差的隨機性可能給芯片帶來難以預(yù)料的后果,而在信息安全領(lǐng)域,工藝偏差的隨機性卻具有很高的應(yīng)用價值。工藝偏差是集成電路制造過程的必然產(chǎn)物,其隨機性來源于制造過程中固有的各種不可控因素。通過工藝偏差相關(guān)參數(shù)的提取,可以形成每個芯片獨特的參數(shù)標識,從而為日益普及的智能終端的身份識別等提供一個有效的解決方案。本文圍繞集成電路工藝偏差的片上檢測與應(yīng)用展開了以下幾方面的研究:1.首先提出一種全新的片上電容陣列測量方法,實現(xiàn)集成電路片上電容參數(shù)的大規(guī)模高精度測量,從而實現(xiàn)對片上電容偏差的檢測。工藝偏差檢測對樣本數(shù)量和測量精度有很高要求。片上電容陣列測量方法通過層次化的系統(tǒng)結(jié)構(gòu)設(shè)計,利用電容陣列測量單元和多路模擬通道選擇單元,實現(xiàn)少量芯片面積開銷下的大規(guī)模高精度電容檢測。電容陣列測量單元采用基于充放電的電容測量方法,在精確的信號控制下確保電容測量精度符合需求。本文在180納米的CMOS工藝下實現(xiàn)了片上電容陣列測量的原型芯片。芯片的測量結(jié)果顯示,電容測量精度達到1fF。本文還給出了芯片電容偏差的分布情況,并對影響電容測量結(jié)果的相關(guān)因素進行分析和比較。片上電容陣列測量方法所采用的系統(tǒng)層次結(jié)構(gòu)可以很容易地推廣到其他靜態(tài)參數(shù)的片上檢測,具有很強的靈活性和通用性。2.在靜態(tài)參數(shù)片上檢測的研究基礎(chǔ)上,進一步提出一種全新的片上高精度時序參數(shù)測量方法,解決片外電學(xué)測量方法無法實現(xiàn)高精度時序參數(shù)測量的問題。時序參數(shù)對靜態(tài)參數(shù)作用于時序信號后所產(chǎn)生的響應(yīng),包括信號上升沿時間、下降沿時間和傳輸延時等。片上高精度時序參數(shù)測量方法采用全新的結(jié)合等效時間采樣和實時采樣的測量結(jié)構(gòu),實現(xiàn)信號時序信息皮秒精度的片上檢測。時域放大器是實現(xiàn)等效時間采樣的主要單元,其在采樣信號的控制下實現(xiàn)對待測波形信號在時域上的放大,然后通過對放大后的波形進行過采樣、濾波和模數(shù)轉(zhuǎn)換等操作,生成最終的數(shù)據(jù)信息。本文在180納米的CMOS工藝下實現(xiàn)了片上高精度時序參數(shù)測量的原型芯片。從芯片的測量結(jié)果中可以得出高精度實測邊沿波形,從波形中可以得到精確的邊沿時間偏差分布。本文利用片上高精度時序參數(shù)測量方法,首次測得觸發(fā)器建立時間和保持時間的偏差分布情況。3.通過工藝偏差片上檢測技術(shù)的研究和工藝偏差相關(guān)特性的分析,本文提出一種全新的物理不可克隆散列函數(shù)的概念。物理不可克隆散列函數(shù)是基于硬件實現(xiàn)的散列函數(shù),它利用工藝偏差的隨機性來實現(xiàn)散列映射。參照算法加密散列函數(shù)的相關(guān)運算和多輪散列操作,物理不可克隆散列函數(shù)可以根據(jù)任意長度的輸入激勵生成固定長度的輸出響應(yīng),從而利用有限的資源開銷生成無窮多的激勵-響應(yīng)對,使其在實際應(yīng)用中的安全性得到極大的提高。本文在180納米的CMOS工藝下實現(xiàn)了物理不可克隆散列函數(shù)的原型芯片。通過芯片的測量和評估,對物理不可克隆散列函數(shù)的獨特性、可靠性和散列映射中的抗碰撞性進行分析。物理不可克隆散列函數(shù)還具有無法復(fù)制、難以實現(xiàn)逆向破解等特性,使其在信息安全應(yīng)用中具備了很強的競爭力。
[Abstract]:With the development of semiconductor industry, technology feature size shrinking, chip integration continues to improve, integrated circuit design and manufacturing complexity is also increasing. When the feature size of the device into the nano scale, process variations have great influence on the performance of the device, seriously restrict the performance of an integrated circuit, power consumption and rate of finished products. Detection technology. The deviation is a hot research field of semiconductor technology, it relies on the measurement of parameters. The static parameters and timing parameters are two factors characterizing process deviation. Through the parameter extraction, can analyze the distribution of chip process variation, establish related model, revise and improve the process steps, thereby to reduce process variation, accelerate the development of new technology progress. Random process variations may bring to chip There's no telling the consequences, and in the field of information security, process deviation The randomness has very high application value. The deviation is the inevitable product of integrated circuit manufacturing process, the various sources of randomness inherent in the manufacturing process of uncontrollable factors. Through the extraction process deviation related parameters, parameter identification of each chip can form a unique, so as to provide an effective solution for intelligent the growing popularity of the terminal identification. This paper focuses on the integrated circuit process deviation on chip detection and application of the following aspects: 1. first proposed a new on-chip capacitor array measurement method, high precision measurement of large-scale integrated circuit chip capacitor parameters, so as to realize the detection of Capacitance Deviation on chip the process deviation detection of sample quantity and the measurement accuracy is very high. The system structure design of capacitor array measurement sheet through the hierarchy, using capacitor array The measurement unit and the analog channel selection unit, to achieve large-scale high-precision capacitance detect small chip area overhead. The capacitor array measuring unit uses capacitance measurement method based on charge and discharge, the control signal under accurate capacitance to ensure measurement accuracy meets the requirements. This paper implements a prototype chip capacitor array measurement on a sheet of CMOS 180 nanometer process under the chip measurement results showed that the capacitance measurement accuracy of 1fF. the distribution of chip capacitance deviation is given, and the related factors affecting the capacitance measurement results were analyzed and compared. The hierarchical structure of on-chip capacitor array measurement method can be easily extended to other static parameters on chip detection basic research, with strong flexibility and versatility of.2. detection in static parameters on chip, proposed a new on-chip high Method of measuring accuracy of timing parameters, solve the method of electrical measurement chip can be realization of high precision timing measurement. Response timing parameters on the static parameters in the timing signal generated by the signal, including the rise time, fall time and transmission delay. The high precision timing parameter measurement method based on equivalent time sampling based on chip the structure and measurement of real time sampling new, detect signal timing information of picosecond precision on chip. The time domain is the main amplifier unit to realize equivalent time sampling, the control of the sample signal to be amplified under the measured waveform signal in the time domain, and then through the enlarged waveform sampling, filtering and analog-to-digital conversion operation, to generate the final data. This paper implements a prototype chip high precision timing parameters on a sheet of CMOS 180 nanometer process chip from. The measurement results can be obtained in the high accuracy edge waveform, waveform can be obtained from the edge of time deviation distribution accurately. Using high precision timing parameter measurement method on the measurement and analysis for the first time to trigger setup time and hold time deviation distribution of.3. through the research and process deviation detection technology process deviation on the related the characteristics, the paper puts forward the concept of a new physical unclonable hash function. Physical unclonable hash function is a hash function based on hardware, it uses random process deviation to achieve hash mapping. Correlation algorithm according to cryptographic hash functions and multiple hash operations, physical unclonable hash function according to the arbitrary length of the input output of fixed length response, thereby generating an infinite number of incentive to response with limited resource overhead, The safety in the practical application has been greatly improved. This paper implements a prototype chip physical unclonable hash function in CMOS 180 nanometer process. Through the measurement and evaluation of the chip, the unique physical unclonable hash function, collision resistance and reliability analysis of hash mappings. Physical unclonable hash function has not copy, it is difficult to achieve reverse break and other characteristics, the application of information security has very strong competitive power.

【學(xué)位授予單位】：浙江大學(xué)
【學(xué)位級別】：博士
【學(xué)位授予年份】：2016
【分類號】：TN407

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