本文關鍵詞：集成電路新型ESD防護器件研究　出處：《浙江大學》2016年博士論文　論文類型：學位論文

  更多相關文章： 集成電路 ESD防護器件設計 GGISCR器件 組件級ESD防護 系統(tǒng)級ESD防護

【摘要】：集成電路的ESD (Electrostatic Discharge)防護設計是提高集成電路和電子系統(tǒng)可靠性的重要關鍵技術。本文分析了集成電路ESD防護設計及其應用背景,提出了新穎的ESD防護器件,滿足了應用領域新技術的要求,并借助理論分析和TCAD (Technology Computer Aided Design)仿真設計研究了器件的工作機理,對有關結果進行流片實驗和測試驗證。具體研究內容和創(chuàng)新點如下：1.提出了基于0.35μm CMOS工藝的新型GGISCR (Gate-Grounded-nMOS Incorporated Silicon Controlled Rectifier)器件,相比目前通用的LVTSCR (Low Voltage Triggered Silicon Controlled Rectifier)器件,在不增加器件面積、不降低器件魯棒性的前提下可將維持電壓提升到7.9V,40μm寬度的GGISCR器件的失效電流達到4.4A,解決了傳統(tǒng)ESD防護器件在器件面積、魯棒性和維持電壓三者之間折中矛盾的關鍵難題。論文借助使用TCAD仿真工具,研究了器件在ESD應力下的直觀重要物理量,包括：電場、電流密度和碰撞離化率等,結合上述結果對其工作機制進行分析和闡述。有關結果發(fā)表在TED期刊,并申請發(fā)明專利。2.提出了基于0.35μm 40V BCD (Bipolar CMOS DMOS)工藝的改進型GGISCR器件,通過優(yōu)化器件結構和并聯(lián)小尺寸GGLDMOS (gate-grounded Lateral Double-diffused MOS)器件,完整地驗證了其ESD防護的有效性,該設計成功應用于某上市公司的電源管理芯片的電源鉗位單元。主要的創(chuàng)新點是基于BCD工藝的特點進一步縮小了器件的回滯窗口,失效電流達到3.5A。通過堆疊的方式極大地提高了器件的維持電壓,解決了電源鉗位單元存在的閂鎖問題,滿足18V和24V電源應用,技術指標優(yōu)越。3.設計了一種新型ESD防護器件FP-LDMOS-SCR (Floating P+Lateral Double-diffused MOS Silicon Controlled Rectifier)器件,用于0.35μm 40V BCD工藝I/O接口的ESD防護。通過在LDMOS器件漏端設計浮空P+區(qū),將器件的失效電流提升到2.7A,且不影響器件正常工作的I-V特性。FP-LDMOS-SCR器件提升了高壓I/O接口的ESD魯棒性且降低了閂鎖風險。有關結果發(fā)表在MR期刊。4.在0.35μm 80V BCD工藝平臺上設計了LDMOS-SCR器件,解決了傳統(tǒng)LDMOS器件在ESD應力下出現(xiàn)過早失效的關鍵難題。TLP測得LDMOS-SCR器件失效電流值為4.3A。通過在漏端插入一個場氧結構,將LDMOS-SCR器件的擊穿電壓從92V提升到99V,進一步增強了器件耐壓特性。5.設計了具有超高魯棒性的ESD防護器件,其失效電流高達18.9A,滿足IEC61000-4-2 15KV接觸放電的ESD防護等級。主要的創(chuàng)新點是在對GGISCR器件的失效機理分析的基礎上,設計了高效的圓形版圖器件,其FOM(Figure of Merit)值為137AV/pF,比常規(guī)的多指條型版圖性能提升73%,技術指標遠優(yōu)于目前業(yè)界的主流產品,有關結果已申請發(fā)明專利。6.設計了一種新型的穿通型五層N++P+PP+N++結構的TVS (Transient Voltage Suppressor)器件。其十二指條型器件獲得超過10A的失效電流,不大于0.17pF的寄生電容,解決了傳統(tǒng)TVS器件寄生電容過大影響系統(tǒng)信號完整性的問題,滿足諸如USB3.0和HDMI1.4高速接口的系統(tǒng)級ESD防護應用,技術指標遠優(yōu)于目前業(yè)界的主流產品。有關結果投稿IEEJ期刊(已錄用),并申請發(fā)明專利。
[Abstract]:Integrated circuit ESD (Electrostatic Discharge) is a key technique to improve protection design reliability of integrated circuit and electronic system. This paper analyzes the design of integrated circuit ESD protection and its application background, put forward the ESD protection device novel, meet new application technical requirements, and by means of theoretical analysis and TCAD (Technology Computer Aided Design) simulation design studies the working mechanism of the device, carried out experiments and tests to verify the results. The specific contents are as follows: 1. novel GGISCR 0.35 m based on CMOS Technology (Gate-Grounded-nMOS Incorporated Silicon Controlled Rectifier) device, compared to the current general LVTSCR (Low Voltage Triggered Silicon Controlled Rectifier) device. Without increasing device area, robustness under the premise of the device will maintain the voltage up to 7. is not reduced 9V, the failure of current GGISCR device 40 m width up to 4.4A, to solve the traditional ESD protection devices in the device area, the key problem of compromise the contradiction between robustness and maintain the voltage of three. With the use of TCAD simulation tools, on the device under stress directly important physical quantities in ESD include: electric field. The current density and the impact ionization rate, combined with the results of its work mechanism is described and analyzed. The results were published in the Journal TED, the invention patent.2. proposed 0.35 m 40V based on BCD (Bipolar CMOS DMOS) and the application of improved GGISCR device technology, through the optimization of device structure and parallel small size GGLDMOS (gate-grounded Lateral Double-diffused MOS devices), to validate the effectiveness of ESD protection, the power management chip design is successfully applied to a listed company in the power clamp unit. The main innovations are based The characteristics of BCD technology in further reducing the device hysteresis window, failure current reaches 3.5A. by stacking method greatly improves the device to maintain the voltage, solve the existing power clamp unit latch, meet the requirements of 18V and 24V power applications, technical superiority index.3. design of a new type of ESD protection device FP-LDMOS-SCR (Floating P+Lateral Double-diffused MOS Silicon Controlled Rectifier) devices, ESD protection for 0.35 m 40V BCD process I/O interface. Through the design of floating drain area of P+ on the LDMOS device, the device failure current up to 2.7A, the I-V characteristics of.FP-LDMOS-SCR devices and does not affect the normal working of the device to enhance the robustness of ESD high voltage I/O interface and reduce the latch risk. Relevant results published in the MR Journal.4. 0.35 m 80V BCD technology platform is designed to solve the traditional LDMOS-SCR devices, LDMOS devices in ESD Under the.TLP key problem of premature failure of the measured current value of 4.3A. LDMOS-SCR device failure through the drain into a field oxide structure, the breakdown voltage of LDMOS-SCR devices increased from 92V to 99V, to further enhance the breakdown voltage characteristics of.5. design with ESD protection device of high robustness, high current failure up to 18.9A, to meet the ESD protection grade IEC61000-4-2 15KV contact discharge. The main innovation is the basis of analysis on the failure mechanism of GGISCR devices on the design of the circular layout device with high efficiency, the FOM (Figure of Merit) is 137AV/ pF, a 73% more than the conventional lifting type layout performance, technical index is far better than the current mainstream products in the industry, the relevant results have been applied to a new five layer through the N++P+PP+N++ structure of TVS.6. (Transient Voltage design patent Suppressor). The twelve refers to the device type A failure current is more than 10A, not more than the parasitic capacitance of 0.17pF, to solve the traditional TVS devices too large parasitic capacitance effect system of signal integrity, meet system level ESD protection applications such as USB3.0 and HDMI1.4 high speed interface, technical index is far better than the current mainstream industry products. The results contribute IEEJ Journal (accepted), and apply for a patent.

【學位授予單位】：浙江大學
【學位級別】：博士
【學位授予年份】：2016
【分類號】：TN40

【相似文獻】

相關期刊論文 前5條

1 周紹文;半導體電磁脈沖防護器件性能測試[J];微電子學與計算機;1989年12期

2 徐斌裕,張利華;硬限幅防護器件參數(shù)測量方法[J];微電子學;1988年06期

3 張希軍;楊潔;王振興;李賢軍;;微帶線在快速脈沖防護器件性能測試中的應用[J];廣東工業(yè)大學學報;2011年03期

4 謝鋒;結合供電線路的制式合理選擇避雷器[J];郵電設計技術;2001年06期

5 ;[J];;年期

相關重要報紙文章 前1條

1 本報記者 趙艷秋;ESD器件：新接口市場是熱點 集成EMI方案將流行[N];中國電子報;2009年

相關博士學位論文 前3條

1 曾杰;集成電路新型ESD防護器件研究[D];浙江大學;2016年

2 鄢永明;靜電放電及其防護器件研究[D];湖南大學;2016年

3 梁海蓮;集成電路高壓ESD防護器件的研究[D];江南大學;2014年

相關碩士學位論文 前3條

1 畢秀文;高壓集成電路的ESD防護器件設計與研究[D];江南大學;2016年

2 王煒槐;納米集成電路ESD防護研究[D];浙江大學;2016年

3 崔強;集成電路中ESD防護研究[D];浙江大學;2008年

，

本文編號：1388418