【摘要】：由于微電子學和集成電路技術(shù)等電子科學相關(guān)技術(shù)不斷進步,航天領(lǐng)域的衛(wèi)星小型化、集成化也隨之發(fā)展起來,小衛(wèi)星已成為世界航天活動高速發(fā)展的主要驅(qū)動力和重要發(fā)展領(lǐng)域。近年來,國際各類研究機構(gòu)對小衛(wèi)星領(lǐng)域開展了大量預言性和探索性的研究。其中最具代表性的便是美國“芯片衛(wèi)星”(Chip Sat)項目,該項目將航天微系統(tǒng)技術(shù)從單一部件級提升到整顆衛(wèi)星的級別,加速了航天飛行器設計向超小型化方向的發(fā)展。空間綜合電子系統(tǒng)是整個衛(wèi)星的核心,也是芯片衛(wèi)星工程設計的重點。而其中的空間數(shù)據(jù)網(wǎng)絡作為數(shù)據(jù)可靠和實時傳輸?shù)闹饕ǖ?在整個系統(tǒng)中的作用同樣重要。Space Wire作為歐洲多家科研機構(gòu)聯(lián)合推出的一套高速、串行,全雙工的數(shù)據(jù)網(wǎng)絡標準,目前已經(jīng)在多個空間任務中得到成功的應用。本文在充分調(diào)研的基礎上,闡述了Space Wire總線的國內(nèi)外應用發(fā)展現(xiàn)狀,特別對Space Wire相關(guān)芯片研制情況進行了重點介紹,之后著重論述了Space Wire基礎協(xié)議以及上層RMAP協(xié)議的特點和工作機制,明確了本文的研究方向和主要工作內(nèi)容。首先,針對Space Wire總線網(wǎng)絡化的特點并結(jié)合芯片應用中的實際問題,搭建Space Wire網(wǎng)絡通信的數(shù)學模型,推導出一套關(guān)鍵通信節(jié)點的計算方法和緩存分配算法,實現(xiàn)對網(wǎng)絡中每個路由節(jié)點的緩存容量進行優(yōu)化配置。其次,針對星載數(shù)據(jù)網(wǎng)絡中大容量存儲單元特有的工作機制,討論Space Wire總線和大容量存儲單元中數(shù)據(jù)流工作特點,提出了一種專用于大容量存儲的Space Wire傳輸層協(xié)議標準。其簡化了繁瑣的數(shù)據(jù)包操作過程,降低了網(wǎng)絡擁塞的可能性,提高了整個Space Wire網(wǎng)絡的性能。通過前面的研究與分析并結(jié)合實際應用中數(shù)據(jù)傳輸需求,提出了一套Space Wire數(shù)據(jù)網(wǎng)絡系統(tǒng),重點表述了Space Wire載荷終端和管理終端兩大核心單元的結(jié)構(gòu)設計。最后,依據(jù)相關(guān)研究、分析、設計和驗證,完成了Space Wire總線控制器在“龍芯”處理器芯片里的集成設計。在有限的資源條件下實現(xiàn)了Space Wire協(xié)議的節(jié)點和路由器設計。每個節(jié)點支持最高400Mbps的數(shù)據(jù)流處理;整個控制器實現(xiàn)了對每個節(jié)點獨立的控制和管理,提高了整個Space Wire控制器在使用過程中的靈活性。本課題對Space Wire總線在芯片衛(wèi)星中的關(guān)鍵技術(shù)進行了研究與分析。其所具有的高傳輸率、高可靠性、通用性、網(wǎng)絡化能夠很好的滿足芯片衛(wèi)星以及未來航天領(lǐng)域?qū)Ω咚倏偩�的需求;對Space Wire網(wǎng)絡層和傳輸層的研究為總線延時可控提供了有效的解決方案;基于“龍芯”的Space Wire控制器設計則在芯片化的道路上邁出了重要一步。本課題的工作具有較強的實際意義,同時對未來Space Wire技術(shù)的相關(guān)研究,具有啟發(fā)和借鑒意義。
[Abstract]:As a result of the continuous progress in electronic science related technologies such as microelectronics and integrated circuit technology, satellite miniaturization in the space field and integration have also developed. Small satellites have become the main driving force and important development field of the rapid development of space activities in the world. In recent years, various international research institutions have carried out a large number of predictive and exploratory research in the field of small satellites. One of the most representative is the "chip satellite" (Chip Sat) project of the United States. This project promotes the technology of space microsystem from the single component level to the whole satellite level, and accelerates the development of spacecraft design to the direction of super miniaturization. The space integrated electronic system is the core of the whole satellite and the key point of the chip satellite engineering design. As the main channel of reliable and real-time data transmission, the spatial data network plays an equally important role in the whole system. Space Wire is a set of high-speed, serial and full-duplex data network standards that are jointly developed by many European scientific research institutions. It has been successfully applied in many space missions. On the basis of full investigation, this paper expounds the current situation of the application of Space Wire bus at home and abroad, especially introduces the development of Space Wire related chips. After that, the characteristics and working mechanism of Space Wire basic protocol and upper RMAP protocol are discussed, and the research direction and main work content of this paper are clarified. Firstly, according to the characteristics of Space Wire bus network and the practical problems in chip application, the mathematical model of Space Wire network communication is built, and a set of calculation method and buffer allocation algorithm of key communication nodes are deduced. The cache capacity of each routing node in the network is optimized. Secondly, aiming at the special working mechanism of mass storage unit in spaceborne data network, this paper discusses the characteristics of data flow in Space Wire bus and mass storage cell, and proposes a Space Wire transport layer protocol standard for mass storage. It simplifies the process of packet operation, reduces the possibility of network congestion, and improves the performance of the whole Space Wire network. Through the previous research and analysis and combining with the data transmission requirement in practical application, a set of Space Wire data network system is proposed, and the structure design of two core units of Space Wire load terminal and management terminal is described emphatically. Finally, according to the related research, analysis, design and verification, the integrated design of Space Wire bus controller in the "Godson" processor chip is completed. The node and router design of Space Wire protocol is implemented under the condition of limited resources. Each node supports the data flow processing of the highest 400Mbps, and the whole controller realizes the independent control and management of each node, and improves the flexibility of the whole Space Wire controller in the process of using. In this paper, the key technology of Space Wire bus in chip satellite is studied and analyzed. Its high transmission rate, high reliability, versatility, networking can well meet the chip satellite and the future aerospace field of high-speed bus requirements; The research of Space Wire network layer and transmission layer provides an effective solution for bus delay control, and the design of Space Wire controller based on "Dragon son" is an important step on the way of chip. The work of this paper is of great practical significance and enlightening and referential to the related research of Space Wire technology in the future.
【學位授予單位】：中國科學院大學(中國科學院國家空間科學中心)
【學位級別】：博士
【學位授予年份】：2017
【分類號】：V443

【參考文獻】

相關(guān)期刊論文 前10條

1 周玉霞;許冬彥;;從標準化角度看小衛(wèi)星商業(yè)化發(fā)展[J];航天標準化;2016年04期

2 董瑤海;;風云四號氣象衛(wèi)星及其應用展望[J];上海航天;2016年02期

3 李艷春;李曉娟;關(guān)永;王瑞;張杰;魏洪興;;基于xMAS模型的SpaceWire信譽邏輯的形式化驗證[J];計算機科學;2016年02期

4 趙云富;吳一帆;孫強;許娜;吳軍;;SpaceWire總線的流量控制機制研究[J];微電子學與計算機;2016年01期

5 王小強;孫宇;;SpaceWire系統(tǒng)芯片測試技術(shù)[J];電子產(chǎn)品可靠性與環(huán)境試驗;2015年05期

6 王瑞;李國良;李戰(zhàn)懷;;基于SpaceWire的AOS系統(tǒng)仿真研究[J];小型微型計算機系統(tǒng);2015年07期

7 周淵;范裕子;周欽;張偉;;基于SpaceWire路由的節(jié)點速率約束條件分析[J];空間電子技術(shù);2015年03期

8 余慶豐;張曉宇;安虹霖;;CSPW:一種改進型SpaceWire總線設計[J];云南民族大學學報(自然科學版);2015年03期

9 徐浩;王同桓;劉振星;雷勇;毛一嵐;;ECSS的包應用標準及其應用[J];航天器工程;2015年02期

10 朱曉燕;陶利民;張偉功;底素然;;面向衛(wèi)星數(shù)據(jù)系統(tǒng)的SpaceWire應用模型仿真研究[J];小型微型計算機系統(tǒng);2015年03期

相關(guān)博士學位論文 前3條

1 閆夢婷;SpaceWire總線RMAP協(xié)議的實現(xiàn)與網(wǎng)絡性能研究[D];中國科學院國家空間科學中心;2016年

2 程愛蓮;片上網(wǎng)絡的建模仿真與性能優(yōu)化研究[D];浙江大學;2012年

3 周慶瑞;IEEE1394鏈路層控制芯片IP核的開發(fā)及IEEE1394總線可靠性的研究[D];中國科學院研究生院（空間科學與應用研究中心）;2008年

相關(guān)碩士學位論文 前10條

1 任文婷;面向SoC應用的AXI總線設計[D];北京理工大學;2014年

2 鐘雪燕;基于FPGA的SpaceWire路由器的設計與驗證[D];南京航空航天大學;2013年

3 毛寧元;SpaceWire冗余網(wǎng)絡關(guān)鍵技術(shù)研究[D];哈爾濱工業(yè)大學;2012年

4 陳熙之;基于SpaceWire標準的星上總線網(wǎng)絡設計[D];哈爾濱工業(yè)大學;2012年

5 周華章;基于SpaceWire的遠程存儲訪問協(xié)議的研究與實現(xiàn)[D];首都師范大學;2012年

6 陳川;基于SpaceWire總線技術(shù)的網(wǎng)絡路由演化算法研究[D];首都師范大學;2012年

7 吳侃;星載并行系統(tǒng)主從式互連總線容錯技術(shù)研究[D];國防科學技術(shù)大學;2011年

8 魯文帥;SpaceWire即插即用技術(shù)研究[D];哈爾濱工業(yè)大學;2011年

9 劉偉偉;SpaceWire路由器研制[D];哈爾濱工業(yè)大學;2011年

10 張玉鳳;基于ARM7的輕小型化數(shù)據(jù)管理系統(tǒng)設計研究[D];中國科學院研究生院（空間科學與應用研究中心）;2011年

，

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