本文關(guān)鍵詞：基于CPCIe的高速多通道信號(hào)采集板卡的設(shè)計(jì)　出處：《中北大學(xué)》2016年碩士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： CPCIe 高速 多通道 信號(hào)采集 DDR3 SDRAM

【摘要】：隨著國(guó)家對(duì)大數(shù)據(jù)化戰(zhàn)略的大力發(fā)展,萬(wàn)物互連的時(shí)代悄然來(lái)臨。而雷達(dá)作為信號(hào)采集傳輸?shù)妮d體,能夠?qū)崿F(xiàn)更遠(yuǎn)、更快、更精確的數(shù)據(jù)采集和處理。高速信號(hào)采集板卡又作為雷達(dá)的重要組成部分,在空間探索領(lǐng)域已經(jīng)變得越來(lái)越重要。為了能夠及時(shí)精準(zhǔn)的捕獲高空被探索物體的各項(xiàng)數(shù)據(jù),對(duì)于高速多通道的信號(hào)采樣技術(shù)的研究就具有越來(lái)越多的現(xiàn)實(shí)意義。通過(guò)對(duì)高速總線技術(shù)和多路信號(hào)采樣實(shí)現(xiàn)方式的研究,文中提出了一種基于CPCIe架構(gòu)的高速多通道信號(hào)采集板卡的設(shè)計(jì)方案。方案中使用了xilinx公司virtex-6系列的FPGA作為主控制器,以TI公司推出的高性能雙通道ADC、DAC轉(zhuǎn)換芯片為信號(hào)采集回放單元,結(jié)合多片大容量的DDR3 SDRAM作為高速緩存單元,采用FPGA內(nèi)部集成的PCIe硬核解決方案來(lái)構(gòu)建CPCIe總線接口單元。文中對(duì)信號(hào)采集板卡的軟硬件進(jìn)行了詳細(xì)的介紹。采用了自頂向下的設(shè)計(jì)思路,對(duì)各個(gè)單元進(jìn)行了全面的仿真、測(cè)試和驗(yàn)證。板卡最高可以在100MHz采樣頻率下同時(shí)對(duì)4路模擬量信號(hào)進(jìn)行采集和傳輸,PCIe接口數(shù)據(jù)上傳速率不低于800MBps。針對(duì)板卡應(yīng)用領(lǐng)域的特殊性,不僅通過(guò)軟件平臺(tái)對(duì)CPCIe高速信號(hào)采集板卡進(jìn)行了功能測(cè)試,還對(duì)板卡進(jìn)行了各種環(huán)境下的硬件測(cè)試。實(shí)驗(yàn)證明,設(shè)計(jì)的CPCIe高速多通道信號(hào)采集板卡能夠很好的滿足系統(tǒng)的需求,可以進(jìn)入試用階段。
[Abstract]:With the great development of the national strategy of big data, the age of interconnection of all things has come quietly. As the carrier of signal acquisition and transmission, radar can realize further and faster. More accurate data acquisition and processing. High speed signal acquisition board as an important part of radar. In the field of space exploration, it has become more and more important. In order to capture the data of the objects being explored from high altitude in time and precision. The research of high-speed multi-channel signal sampling technology has more and more practical significance. Through the research of high-speed bus technology and multi-channel signal sampling implementation. In this paper, a design scheme of high-speed multi-channel signal acquisition board based on CPCIe architecture is presented, in which the FPGA of virtex-6 series of xilinx company is used as the main controller. The high performance dual-channel ADC-DAC conversion chip of TI is used as the signal acquisition and playback unit, and the multi-chip DDR3 SDRAM is used as the cache unit. The CPCIe bus interface unit is constructed by using the PCIe hard core solution integrated within FPGA. The hardware and software of the signal acquisition board are introduced in detail. The top-down design idea is adopted. . All units are simulated, tested and verified. The card can collect and transmit four analog signals simultaneously at 100MHz sampling frequency. The data upload rate of PCIe interface is not less than 800MBps.In view of the particularity of the application field of board card, not only the function of CPCIe high-speed signal acquisition board is tested through software platform. The hardware of the board is also tested in various environments. The experiment shows that the CPCIe high-speed multi-channel signal acquisition board can meet the needs of the system and can enter the trial stage.
【學(xué)位授予單位】：中北大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2016
【分類號(hào)】：TP274

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