超聲探測(cè)器多通道數(shù)據(jù)獲取系統(tǒng)的設(shè)計(jì)
發(fā)布時(shí)間：2018-12-15 03:42
【摘要】：超聲診斷是一項(xiàng)重要的醫(yī)學(xué)診斷技術(shù),由于它具有無(wú)痛、無(wú)創(chuàng)、操作方便、顯示直觀、成本低廉等特點(diǎn),在醫(yī)學(xué)診斷領(lǐng)域得到了廣泛的應(yīng)用。就超聲診斷技術(shù)而言,超聲波的頻率越高,圖像分辨率就越高,顯示的結(jié)構(gòu)也越精細(xì)。傳統(tǒng)的超聲探測(cè)器探測(cè)的超聲波頻率較低,導(dǎo)致圖像分辨率低,成像精度差,制約了超聲診斷技術(shù)的發(fā)展。因此,探索高分辨率超聲探測(cè)器成為近年來(lái)研究熱點(diǎn)。PVDF壓電膜具有壓電效應(yīng),當(dāng)接收到超聲信號(hào)時(shí)會(huì)有感應(yīng)電荷產(chǎn)生。本實(shí)驗(yàn)室自主研發(fā)的Topmetal像素傳感器芯片具有體積小、位置分辨率高、響應(yīng)速度快等優(yōu)勢(shì),并且可以用來(lái)收集電荷,產(chǎn)生模擬電信號(hào)輸出。因此,利用PVDF壓電膜和Topmetal像素傳感器可以設(shè)計(jì)出滿(mǎn)足需求的高分辨率超聲探測(cè)器。本文的研究重點(diǎn)就是為此超聲探測(cè)器設(shè)計(jì)多通道數(shù)據(jù)獲取系統(tǒng)。該數(shù)據(jù)獲取系統(tǒng)通過(guò)8通道、12位高速模數(shù)轉(zhuǎn)換器對(duì)像素傳感器模擬輸出進(jìn)行采樣,采樣率為25MSPS。ADC采樣的數(shù)據(jù)以LVDS形式傳送到FPGA后,經(jīng)過(guò)差分到單端的轉(zhuǎn)換、延時(shí)調(diào)整、串并轉(zhuǎn)換、FIFO緩存后寫(xiě)入128MByte的SDRAM中,然后通過(guò)PCIe總線將數(shù)據(jù)傳送到PC端保存并分析。PC端的控制指令通過(guò)PCIe總線傳送到FPGA中。本文的主要研究工作：1、硬件電路設(shè)計(jì)：包括芯片bonding板、芯片驅(qū)動(dòng)板、ADC采樣板的硬件電路設(shè)計(jì)。bonding板實(shí)現(xiàn)芯片pad的引出。驅(qū)動(dòng)板提供芯片控制信號(hào)、外部復(fù)位電平和模擬輸出驅(qū)動(dòng)。ADC采樣板用來(lái)對(duì)像素傳感器的模擬輸出進(jìn)行采樣。2、系統(tǒng)邏輯設(shè)計(jì)：包括時(shí)鐘管理模塊、ADC寄存器配置模塊、差分轉(zhuǎn)換模塊、延時(shí)控制模塊、串并轉(zhuǎn)換模塊、數(shù)據(jù)緩存模塊以及QSYS系統(tǒng)設(shè)計(jì)。3、系統(tǒng)軟件設(shè)計(jì)：利用Linux操作系統(tǒng)下PCIe驅(qū)動(dòng)用戶(hù)接口函數(shù)實(shí)現(xiàn)了ADC寄存器設(shè)置、數(shù)據(jù)延時(shí)設(shè)置、延時(shí)分析和傳輸誤碼分析等功能。4、系統(tǒng)測(cè)試：包括硬件電子學(xué)各模塊測(cè)試和整個(gè)超聲探測(cè)系統(tǒng)的測(cè)試。測(cè)試結(jié)果表明,數(shù)據(jù)獲取系統(tǒng)可穩(wěn)定工作在25MSPS采樣率下。
[Abstract]:Ultrasonic diagnosis is an important medical diagnosis technology. Because of its painless, non-invasive, convenient operation, visual display, low cost and so on, it has been widely used in the field of medical diagnosis. As far as ultrasonic diagnosis technology is concerned, the higher the ultrasonic frequency, the higher the image resolution and the finer the display structure. The low ultrasonic frequency detected by traditional ultrasonic detectors leads to low image resolution and poor imaging accuracy, which restricts the development of ultrasonic diagnosis technology. Therefore, the exploration of high resolution ultrasonic detectors has become a hot topic in recent years. PVDF piezoelectric film has piezoelectric effect and inductive charge will be generated when the ultrasonic signal is received. The Topmetal pixel sensor chip developed by our laboratory has the advantages of small size, high position resolution, fast response speed, and can be used to collect charge and generate analog electrical signal output. Therefore, high resolution ultrasonic detector can be designed by using PVDF piezoelectric film and Topmetal pixel sensor. The key point of this paper is to design a multi-channel data acquisition system for ultrasonic detector. The data acquisition system samples the analog output of pixel sensor through 8 channels and 12 bits high speed A / D converter. After the data sampled by 25MSPS.ADC is transmitted to FPGA in the form of LVDS, after the difference to single terminal conversion, the delay is adjusted. Series-parallel conversion, FIFO cache, then write to 128MByte SDRAM, and then transfer data to PC through PCIe bus to save and analyze. PC control instructions are sent to FPGA via PCIe bus. The main research work of this paper is as follows: 1. Hardware circuit design: including the hardware circuit design of chip bonding board, chip driver board and ADC sampling board. Bonding board realizes the extraction of chip pad. The driver board provides chip control signal, external reset level and analog output driver. ADC sampling board is used to sample the analog output of pixel sensor. 2. System logic design: including clock management module, ADC register configuration module, Differential conversion module, delay control module, series-parallel conversion module, data cache module and QSYS system design. 3. System software design: using PCIe driver user interface function under Linux operating system to realize ADC register setting. Data delay setting, delay analysis, transmission error analysis and other functions. 4, system testing: including hardware and electronics modules test and the whole ultrasonic detection system testing. The test results show that the data acquisition system can work stably under the 25MSPS sampling rate.
【學(xué)位授予單位】：華中師范大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類(lèi)號(hào)】：TH776
本文編號(hào)：2379902
[Abstract]:Ultrasonic diagnosis is an important medical diagnosis technology. Because of its painless, non-invasive, convenient operation, visual display, low cost and so on, it has been widely used in the field of medical diagnosis. As far as ultrasonic diagnosis technology is concerned, the higher the ultrasonic frequency, the higher the image resolution and the finer the display structure. The low ultrasonic frequency detected by traditional ultrasonic detectors leads to low image resolution and poor imaging accuracy, which restricts the development of ultrasonic diagnosis technology. Therefore, the exploration of high resolution ultrasonic detectors has become a hot topic in recent years. PVDF piezoelectric film has piezoelectric effect and inductive charge will be generated when the ultrasonic signal is received. The Topmetal pixel sensor chip developed by our laboratory has the advantages of small size, high position resolution, fast response speed, and can be used to collect charge and generate analog electrical signal output. Therefore, high resolution ultrasonic detector can be designed by using PVDF piezoelectric film and Topmetal pixel sensor. The key point of this paper is to design a multi-channel data acquisition system for ultrasonic detector. The data acquisition system samples the analog output of pixel sensor through 8 channels and 12 bits high speed A / D converter. After the data sampled by 25MSPS.ADC is transmitted to FPGA in the form of LVDS, after the difference to single terminal conversion, the delay is adjusted. Series-parallel conversion, FIFO cache, then write to 128MByte SDRAM, and then transfer data to PC through PCIe bus to save and analyze. PC control instructions are sent to FPGA via PCIe bus. The main research work of this paper is as follows: 1. Hardware circuit design: including the hardware circuit design of chip bonding board, chip driver board and ADC sampling board. Bonding board realizes the extraction of chip pad. The driver board provides chip control signal, external reset level and analog output driver. ADC sampling board is used to sample the analog output of pixel sensor. 2. System logic design: including clock management module, ADC register configuration module, Differential conversion module, delay control module, series-parallel conversion module, data cache module and QSYS system design. 3. System software design: using PCIe driver user interface function under Linux operating system to realize ADC register setting. Data delay setting, delay analysis, transmission error analysis and other functions. 4, system testing: including hardware and electronics modules test and the whole ultrasonic detection system testing. The test results show that the data acquisition system can work stably under the 25MSPS sampling rate.
【學(xué)位授予單位】：華中師范大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類(lèi)號(hào)】：TH776
【相似文獻(xiàn)】
相關(guān)碩士學(xué)位論文 前1條
1 劉軍;超聲探測(cè)器多通道數(shù)據(jù)獲取系統(tǒng)的設(shè)計(jì)[D];華中師范大學(xué);2015年
，本文編號(hào)：2379902
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