【摘要】：為了支持任意電路上簽名數(shù)據(jù)同態(tài)運算,本文利用陷門采樣技術,基于與門和異或門構造了一個只受電路深度和安全參數(shù)影響的層次全同態(tài)簽名方案。電路生成的新簽名具有公開可驗證性,新簽名尺寸與電路尺寸以及原簽名數(shù)據(jù)的尺寸無關。方案在標準模型下基于格上最短整數(shù)解困難問題可證安全。用戶可以在不知道私鑰的情況下進行指定簽名集合中簽名的層次全同態(tài)運算,已有的研究還主要集中在線性同態(tài)方案和多項式同態(tài)方案。
[Abstract]:In order to support the homomorphism operation of signature data on arbitrary circuits, a hierarchical homomorphic signature scheme based on gate and XOR gates is constructed based on trapdoor sampling technique, which is only affected by circuit depth and security parameters. The new signature generated by the circuit is publicly verifiable, and the size of the new signature is independent of the size of the circuit and the size of the original signature data. The scheme is provable security based on the shortest integer solution on the lattice under the standard model. Users can perform the hierarchical homomorphism operation of the signature in the specified signature set without knowing the private key. The existing researches mainly focus on the linear homomorphism scheme and the polynomial homomorphism scheme.
【作者單位】： 哈爾濱工程大學計算機科學與技術學院;哈爾濱工程大學教務處;哈爾濱工程大學國家保密學院;
【基金】：國家自然科學基金項目(61170241,61472097)
【分類號】：TN918.91

【相似文獻】

相關期刊論文 前10條

1 楊耀增;;用同態(tài)，

本文編號：2281642