【摘要】：通信系統(tǒng)中,通常使用信道編碼來(lái)提高系統(tǒng)性能。Turbo乘積碼(TPC)是一種結(jié)構(gòu)簡(jiǎn)單而且具有良好的誤碼率性能和完整的理論推導(dǎo)的編碼方法。在實(shí)際中得到廣泛的應(yīng)用。現(xiàn)在已經(jīng)有高性能的編譯碼芯片產(chǎn)品被廣泛的應(yīng)用于通信、信息存儲(chǔ)等方面。但是由于技術(shù)的封鎖,國(guó)內(nèi)無(wú)法獲得高性能的Turbo編譯碼芯片。編譯碼芯片在工程中需要主控芯片的驅(qū)動(dòng),并為其分配相應(yīng)的布線空間和I/O資源。因此以合理的算法為基礎(chǔ),通過(guò)FPGA實(shí)現(xiàn)編譯碼系統(tǒng)可以節(jié)省資源,實(shí)現(xiàn)高速并行處理,而且具有良好的可移植性。本文從TPC的基本理論出發(fā),分別對(duì)傳統(tǒng)的理論進(jìn)行分析,通過(guò)研究譯碼參數(shù)對(duì)譯碼輸出的影響。對(duì)現(xiàn)有的譯碼算法從邏輯設(shè)計(jì)的角度進(jìn)行調(diào)整,主要目的是設(shè)計(jì)出譯碼速度高、性能穩(wěn)定以及資源占用小的編譯碼系統(tǒng)。并對(duì)TPC的主流譯碼算法進(jìn)行以下研究:硬判決算法可以運(yùn)用于特殊的單比特傳輸系統(tǒng),并且高信噪比條件下具有良好性能。在FPGA工程實(shí)現(xiàn)中,結(jié)構(gòu)簡(jiǎn)單、譯碼延時(shí)小、資源占用低等特點(diǎn)。在保留以上優(yōu)點(diǎn)的基礎(chǔ)上,采用錯(cuò)誤圖樣調(diào)整并且迭代的方法提高誤碼率性能。本文通過(guò)Matlab仿真驗(yàn)證算法性能,以及FPGA邏輯時(shí)序圖來(lái)進(jìn)一步對(duì)算法進(jìn)行實(shí)現(xiàn)以及結(jié)果驗(yàn)證。在軟判決良好的誤碼率性能的基礎(chǔ)上,研究譯碼過(guò)程中影響譯碼速度和性能的參數(shù)。并通過(guò)Matlab進(jìn)行仿真驗(yàn)證。在盡可能不影響誤碼率性能的情況下,分別從數(shù)學(xué)計(jì)算、譯碼結(jié)構(gòu)、譯碼參數(shù)以及譯碼流程上做出一定的調(diào)整。最終通過(guò)FPGA邏輯優(yōu)化實(shí)現(xiàn)高吞吐率、低資源占用有良好的可移植性的編譯碼系統(tǒng)設(shè)計(jì)。
[Abstract]:In communication systems, channel coding is usually used to improve system performance. Turbo product code (TPC) is a simple coding method with good BER performance and complete theoretical derivation. It is widely used in practice. Nowadays, high performance codec chips have been widely used in communication, information storage and so on. However, due to the blockage of technology, high performance Turbo codec chips can not be obtained in China. Code and decode chips need to be driven by the main control chip in the engineering, and the corresponding wiring space and I / O resources are assigned to them. Therefore, based on the reasonable algorithm, the system can save resources and achieve high speed parallel processing through FPGA, and it has good portability. Based on the basic theory of TPC, this paper analyzes the traditional theory, and studies the effect of decoding parameters on decoding output. The main purpose of adjusting the existing decoding algorithms from the point of view of logic design is to design a codec system with high decoding speed, stable performance and low resource consumption. The main decoding algorithms of TPC are studied as follows: the hard decision algorithm can be applied to special single-bit transmission systems and has good performance under the condition of high signal-to-noise ratio (SNR). In the implementation of FPGA, the structure is simple, the decoding delay is small and the resource is low. On the basis of preserving the above advantages, error pattern adjustment and iterative method are used to improve the bit error rate (BER) performance. In this paper, the performance of the algorithm is verified by Matlab simulation, as well as the FPGA logic sequence diagram to further implement the algorithm and verify the results. On the basis of soft decision with good BER performance, the parameters affecting decoding speed and performance in decoding process are studied. The simulation results are verified by Matlab. Under the condition that the BER performance is not affected as much as possible, some adjustments are made from mathematical calculation, decoding structure, decoding parameters and decoding flow. Finally, the design of code and decode system with high throughput and good portability is realized by FPGA logic optimization.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN911.22;TN791

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