基于安全ASIC密碼芯片PCIE加密卡系統(tǒng)的設(shè)計(jì)與實(shí)現(xiàn)
發(fā)布時(shí)間：2018-08-21 11:10
【摘要】：隨著科技的發(fā)展和社會(huì)的進(jìn)步,傳統(tǒng)接口對(duì)數(shù)據(jù)的傳輸越來(lái)越不能滿足用戶的需求。并且用戶對(duì)數(shù)據(jù)傳輸安全性的認(rèn)知和需求也越來(lái)越高。本設(shè)計(jì)就滿足了用戶大數(shù)據(jù)、高安全性的需求。本文詳細(xì)的闡述了基于國(guó)內(nèi)某款高性能ASIC安全密碼芯片PCIE加密卡系統(tǒng)的設(shè)計(jì)與實(shí)現(xiàn)。本設(shè)計(jì)主要包括兩個(gè)方面:1、FPGA實(shí)現(xiàn)PEX8311芯片與安全ASIC密碼芯片進(jìn)行數(shù)據(jù)交互。開(kāi)發(fā)Verilog HDL代碼,用狀態(tài)機(jī)實(shí)現(xiàn)密碼芯片的時(shí)序要求。并且對(duì)Verilog HDL代碼進(jìn)行仿真測(cè)試,以驗(yàn)證其正確性,實(shí)現(xiàn)真正的數(shù)據(jù)交互。2、在PC端設(shè)計(jì)上位機(jī)軟件,開(kāi)發(fā)C++代碼,并對(duì)上位機(jī)軟件的C++代碼進(jìn)行調(diào)試,測(cè)試與驗(yàn)證,保證其能夠?qū)⒄_的數(shù)據(jù)、地址、命令等發(fā)送到密碼芯片。本設(shè)計(jì)采用PEX8311芯片,實(shí)現(xiàn)上位機(jī)軟件與FPGA芯片進(jìn)行數(shù)據(jù)交互,通過(guò)PEX8311芯片將數(shù)據(jù)發(fā)送到FPGA,在通過(guò)FPGA的內(nèi)部邏輯將數(shù)據(jù)發(fā)送到安全ASIC密碼芯片。實(shí)現(xiàn)了PC端上位機(jī)軟件對(duì)密碼芯片的靈活控制,上位機(jī)軟件向安全ASIC密碼芯片發(fā)送數(shù)據(jù),命令,地址等,操縱密碼芯片的SM2加解密運(yùn)算、SM3運(yùn)算、密鑰協(xié)商等。本設(shè)計(jì)最終形成了PCIE加密卡的最小系統(tǒng),可以讓用戶更加直觀的體驗(yàn)到對(duì)密碼芯片的控制,滿足用戶對(duì)數(shù)據(jù)安全性的需求。本設(shè)計(jì)的創(chuàng)新工作如下:通過(guò)利用PEX8311芯片,FPGA內(nèi)部邏輯,ASIC安全密碼芯片,設(shè)計(jì)成一個(gè)PCIE加密卡的最小系統(tǒng)。實(shí)現(xiàn)的功能是可以傳輸大批量的數(shù)據(jù),并最終對(duì)這些數(shù)據(jù)進(jìn)行SM2算法運(yùn)算和SM3算法運(yùn)算,以確保數(shù)據(jù)的安全性。采用PCIE接口進(jìn)行數(shù)據(jù)傳輸,支持PCIE 1.0a標(biāo)準(zhǔn)。此接口相比于傳統(tǒng)接口,如:USB、SPI、UART等,傳輸?shù)臄?shù)據(jù)量更大,速度更快,可以滿足用戶對(duì)大數(shù)據(jù)傳輸?shù)男枨蟆Ｓ捎赑EX8311芯片與ASIC安全密碼芯片的時(shí)序完全不同,因此本設(shè)計(jì)采用Verilog HDL語(yǔ)言設(shè)計(jì)狀態(tài)機(jī)仿造密碼芯片的時(shí)序要求,以完成PEX8311芯片與密碼芯片的數(shù)據(jù)交互。本設(shè)計(jì)完全站在用戶使用方便快捷,滿足用戶需求的角度來(lái)完成PCIE加密卡系統(tǒng)的設(shè)計(jì)與實(shí)現(xiàn)。
[Abstract]:With the development of science and technology and the progress of society, the traditional interface can not meet the needs of users more and more. Moreover, the users' cognition and demand for data transmission security are more and more high. This design meets the needs of user big data, high security. In this paper, the design and implementation of PCIE encryption card system based on a high performance ASIC secure cipher chip is described in detail. This design mainly includes two aspects: PEX8311 chip and secure ASIC cipher chip. Development of Verilog HDL code, state machine to achieve the timing requirements of the cryptographic chip. The Verilog HDL code is simulated and tested to verify its correctness, to realize real data interaction. 2. To design PC software on PC, develop C code, and debug, test and verify the C code of PC software. Make sure it can send the correct data, address, command and so on to the password chip. The design uses PEX8311 chip to realize the data interaction between host computer software and FPGA chip, sends data to FPGA through PEX8311 chip, and sends data to secure ASIC cipher chip through the internal logic of FPGA. The PC software realizes the flexible control of the cipher chip. The PC software sends data, commands, addresses to the secure ASIC cipher chip, and controls the SM2 encryption and decryption operation of the cipher chip, such as SM3 operation, key agreement and so on. This design finally forms the minimum system of PCIE encryption card, which can make users experience the control of cipher chip more intuitively, and meet the demand of data security. The innovative work of this design is as follows: by using PEX8311 chip to design a minimum system of PCIE encryption card by using PEX8311 internal logic and ASIC security cipher chip. The function is to transmit large quantities of data, and finally carry out SM2 algorithm and SM3 algorithm operation to ensure the security of the data. PCIE interface is used for data transmission, which supports PCIE 1.0a standard. Compared with the traditional interface, such as: USB big data, this interface can transmit more data and faster, so it can meet the needs of users for big data transmission. Because the timing of PEX8311 chip and ASIC security cipher chip is completely different, this design adopts Verilog HDL language to design state machine to simulate the timing requirement of cryptographic chip, in order to complete the data interaction between PEX8311 chip and cipher chip. This design is based on the user's convenience and convenience to meet the user's needs to complete the design and implementation of the PCIE encryption card system.
【學(xué)位授予單位】：遼寧大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN918.4
[Abstract]:With the development of science and technology and the progress of society, the traditional interface can not meet the needs of users more and more. Moreover, the users' cognition and demand for data transmission security are more and more high. This design meets the needs of user big data, high security. In this paper, the design and implementation of PCIE encryption card system based on a high performance ASIC secure cipher chip is described in detail. This design mainly includes two aspects: PEX8311 chip and secure ASIC cipher chip. Development of Verilog HDL code, state machine to achieve the timing requirements of the cryptographic chip. The Verilog HDL code is simulated and tested to verify its correctness, to realize real data interaction. 2. To design PC software on PC, develop C code, and debug, test and verify the C code of PC software. Make sure it can send the correct data, address, command and so on to the password chip. The design uses PEX8311 chip to realize the data interaction between host computer software and FPGA chip, sends data to FPGA through PEX8311 chip, and sends data to secure ASIC cipher chip through the internal logic of FPGA. The PC software realizes the flexible control of the cipher chip. The PC software sends data, commands, addresses to the secure ASIC cipher chip, and controls the SM2 encryption and decryption operation of the cipher chip, such as SM3 operation, key agreement and so on. This design finally forms the minimum system of PCIE encryption card, which can make users experience the control of cipher chip more intuitively, and meet the demand of data security. The innovative work of this design is as follows: by using PEX8311 chip to design a minimum system of PCIE encryption card by using PEX8311 internal logic and ASIC security cipher chip. The function is to transmit large quantities of data, and finally carry out SM2 algorithm and SM3 algorithm operation to ensure the security of the data. PCIE interface is used for data transmission, which supports PCIE 1.0a standard. Compared with the traditional interface, such as: USB big data, this interface can transmit more data and faster, so it can meet the needs of users for big data transmission. Because the timing of PEX8311 chip and ASIC security cipher chip is completely different, this design adopts Verilog HDL language to design state machine to simulate the timing requirement of cryptographic chip, in order to complete the data interaction between PEX8311 chip and cipher chip. This design is based on the user's convenience and convenience to meet the user's needs to complete the design and implementation of the PCIE encryption card system.
【學(xué)位授予單位】：遼寧大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN918.4
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