本文選題：LDPC + 譯碼器　； 參考：《西南交通大學》2017年碩士論文

【摘要】：自從信息論的創(chuàng)始人香農(nóng)(Shannon)在其論文中提出了信道編碼的理念后,學者們就開始投身于研究發(fā)現(xiàn)復雜度低、易于實現(xiàn)且逼近香濃極限的性能優(yōu)異的信道編碼。上個世紀六十年代,麻省理工學院的Robert Gallager第一次提出了 LDPC碼,即低密度奇偶校驗碼(Low Density Parity Check Codes)。但是由于當時的計算能力有限,LDPC一直沒有引起人們的注意,直到1996年,人們才重新發(fā)現(xiàn)了 LDPC碼的優(yōu)異性能。這些年來,FPGA技術(shù)的進步越來越快,并且FPGA具有功能性能強大,開發(fā)周期很短,可以重復進行編程等特點,已成為硬件設(shè)計中的首選器件之一。因此,本文采用FPGA來設(shè)計和實現(xiàn)一種可以合理的兼顧吞吐量、資源和復雜度的LDPC碼編譯碼器。本文將基于二進制LDPC和非二進制LDPC編譯碼器的FPGA設(shè)計和實現(xiàn)展開研究:首先,基于對現(xiàn)有的二進制LDPC碼和非二進制LDPC碼譯碼算法的研究和分析,確定了以硬件實現(xiàn)復雜度較低且性能損失較少的Min-Sum算法和EMS算法分別作為二進制LDPC譯碼器和非二進制LDPC譯碼器FPGA實現(xiàn)的譯碼算法并使用Matlab進行誤碼率仿真。其次,本文確定了部分并行結(jié)構(gòu)作為本文譯碼器的實現(xiàn)結(jié)構(gòu),使用硬件描述語言Verilog以及VHDL進行各模塊實現(xiàn)。另外,為了提高譯碼器的實用性,本文對譯碼器的結(jié)構(gòu)進行了優(yōu)化使其可以靈活配置以支持不同碼率或者碼長的LDPC碼譯碼;為了提高連續(xù)譯碼能力,程序增加了數(shù)據(jù)乒乓操作輸入數(shù)據(jù)存儲功能;為了提高吞吐率,譯碼器沒有固定譯碼迭代次數(shù),并且加入了可以設(shè)置的最大迭代次數(shù),如果在最大迭代次數(shù)內(nèi)完成譯碼,則迭代停止。最后,本文使用Modelsim 6.5C作為仿真工具對編譯碼器進行功能仿真測試,并使用Xilinx ISE 14.6軟件對譯碼器進行綜合及布局布線,目標芯片為:Xilinx XC6VSX315T。對綜合結(jié)果進行分析,本文實現(xiàn)的二進制和非二進制LDPC編譯碼器都具有較高的吞吐率并且復雜度較低,能夠合理的兼顧吞吐量、資源和復雜度。
[Abstract]:Since Shannon, the founder of information theory, put forward the idea of channel coding in his thesis, scholars have begun to devote themselves to the research of channel coding with low complexity, easy to implement and close to the limit of fragrance. In the 1960s, Robert Gallager of the Massachusetts Institute of Technology first proposed LDPC codes, which are called low Density Parity Check codes. However, due to the limited computing power at that time, the excellent performance of LDPC codes was not discovered until 1996. In recent years, the progress of FPGA technology is more and more rapid, and FPGA has the characteristics of powerful function, short development period, and can be repeated programming, which has become one of the first choice devices in hardware design. Therefore, FPGA is used to design and implement a LDPC codec which can reasonably balance throughput, resource and complexity. In this paper, the design and implementation of FPGA based on binary LDPC and non-binary LDPC decoders are studied. Firstly, based on the research and analysis of the existing decoding algorithms of binary LDPC codes and non-binary LDPC codes, The Min-Sum algorithm and the EMS algorithm, which have lower hardware complexity and less performance loss, are chosen as the decoding algorithms of binary LDPC decoder and non-binary LDPC decoder FPGA, respectively, and the BER simulation is carried out with Matlab. Secondly, this paper determines part of the parallel structure as the implementation structure of the decoder, using the hardware description language Verilog and VHDL to implement each module. In addition, in order to improve the practicability of the decoder, the structure of the decoder is optimized so that it can be configured flexibly to support the decoding of LDPC codes with different bit rates or code lengths, and to improve the ability of continuous decoding. The program adds data ping-pong operation input data storage function; in order to improve throughput, the decoder does not have fixed decoding iterations, and adds the maximum number of iterations that can be set, if the decoding is completed within the maximum number of iterations, Then the iteration stops. Finally, this paper uses Modelsim 6.5C as the simulation tool to carry on the function simulation test to the codec, and uses the Xilinx ISE 14.6 software to carry on the synthesis and the layout wiring to the decoder, the target chip is: Xilinx XC6VSX315T. The results show that both binary and non-binary LDPC encoders have high throughput and low complexity, and can reasonably take into account throughput, resource and complexity.
【學位授予單位】：西南交通大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TN911.22;TN791

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本文編號：1814050