本文選題：LDPC碼　切入點：概率計算　出處：《電子科技大學》2017年碩士論文　論文類型：學位論文

【摘要】：LDPC碼是一種重要的線性分組碼,具有逼近香農(nóng)限的特性,已廣泛應用于深空通信、衛(wèi)星通信、無線局域網(wǎng)中,并且成為下一代無線通信系統(tǒng)信道編碼候選方案之一。由于缺乏低代價高性能的譯碼算法,LDPC碼在提出的早期一直未能得到重視。隨著迭代譯碼算法的提出與發(fā)展成熟,提出的BP、LLR BP和Min-Sum等LDPC譯碼算法的復雜度有所降低,但其譯碼器的實現(xiàn)復雜度依舊較高。在傳統(tǒng)的數(shù)值表征和計算方法不能再有效地降低LDPC譯碼器實現(xiàn)復雜度的情況下,概率LDPC譯碼器被提出。通過采用新型的數(shù)值表征和計算方法,可以有效降低LDPC譯碼器的硬件實現(xiàn)復雜度。但是,現(xiàn)有概率計算譯碼方式下的變量節(jié)點(VN)依舊存在數(shù)據(jù)鎖存等問題,將會嚴重制約概率計算的性能;同時,現(xiàn)有概率LDPC譯碼算法的性能較傳統(tǒng)譯碼算法會略有損失。因此,概率LDPC譯碼器的應用實現(xiàn)方面還有很多的問題亟待研究和解決。本文以概率LDPC譯碼器的節(jié)點設計實現(xiàn)、性能提升策略為主要研究內(nèi)容,重點研究了采用包編碼技術(shù)的概率LDPC譯碼算法。首先介紹了概率計算的基本原理,并給出基于線性有限狀態(tài)機利用概率比特序列實現(xiàn)邏輯運算單元的結(jié)構(gòu)和仿真分析;然后回顧了 LDPC碼原理以及其譯碼算法的改進過程,介紹了概率LDPC譯碼算法,詳細描述了解決變量節(jié)點鎖存問題的EM、TFM、MTFM重隨機模塊結(jié)構(gòu),給出了整個譯碼算法框架,并提出了改進譯碼性能的雙路更新EM措施;而后在前期研究基礎上,首次將包編碼技術(shù)應用于概率LDPC譯碼器設計當中;最后設計了概率LDPC譯碼器的實現(xiàn)架構(gòu),采用VHDL編寫了實現(xiàn)四種碼率譯碼器的RTL代碼,并進行了性能仿真驗證。本文的主要工作和創(chuàng)新點如下:(1)針對變量節(jié)點鎖存問題,提出了雙路變量節(jié)點和校驗節(jié)點更新EM的方式,使概率LDPC譯碼算法性能較傳統(tǒng)更新EM的方式有所提升;(2)首次將包編碼技術(shù)應用于概率LDPC譯碼器設計當中,顯著提升了譯碼性能,同時保留了譯碼時延小、復雜度低的優(yōu)勢;(3)在MATLAB軟件平臺上進行了性能仿真驗證及誤比特率和誤塊率分析;采用Simulink和Modelsim協(xié)同仿真進行了概率LDPC譯碼器RTL代碼的功能測試和性能分析。
[Abstract]:LDPC code is an important linear block code with the characteristic of approaching Shannon limit. It has been widely used in deep space communication, satellite communication and wireless local area network (WLAN). It has become one of the candidate schemes for channel coding in the next generation wireless communication system. Due to the lack of low cost and high performance decoding algorithm, LDPC codes have not been paid much attention in the early stage. With the development and development of iterative decoding algorithms, The complexity of the proposed LDPC decoding algorithms such as BP LLRBP and Min-Sum is reduced, but the implementation complexity of the decoder is still high. When the traditional numerical representation and computation methods can no longer effectively reduce the implementation complexity of the LDPC decoder, Probabilistic LDPC decoder is proposed. By using a new numerical representation and calculation method, the hardware implementation complexity of LDPC decoder can be reduced effectively. However, The existing probabilistic LDPC decoding methods still have some problems such as data latch, which will seriously restrict the performance of probabilistic computation, and the performance of the existing probabilistic LDPC decoding algorithm will be slightly reduced compared with the traditional decoding algorithm. Therefore, the performance of the existing probabilistic LDPC decoding algorithm will be slightly lower than that of the traditional decoding algorithm. There are still many problems to be solved in the application of probabilistic LDPC decoder. In this paper, the node design and implementation of probabilistic LDPC decoder and the performance enhancement strategy are the main research contents. The probabilistic LDPC decoding algorithm using packet coding technique is mainly studied. Firstly, the basic principle of probability calculation is introduced, and the structure and simulation analysis of logic operation unit based on linear finite state machine using probabilistic bit sequence are given. Then, the principle of LDPC code and the improvement process of its decoding algorithm are reviewed. The probabilistic LDPC decoding algorithm is introduced. The structure of EMN TFMM-MTFM heavy random module is described in detail, and the whole decoding algorithm framework is given. A dual-channel updating EM method to improve decoding performance is proposed, and then packet coding technology is applied to the design of probabilistic LDPC decoder for the first time on the basis of previous research. Finally, the implementation framework of probabilistic LDPC decoder is designed. The RTL codes of four rate decoders are compiled with VHDL, and the performance simulation is carried out. The main work and innovation of this paper are as follows: 1) aiming at the problem of variable node latching, a method of updating EM between two variable nodes and check node is proposed. The performance of probabilistic LDPC decoding algorithm is better than that of traditional updating EM.) the packet coding technique is applied to the design of probabilistic LDPC decoder for the first time, which improves the decoding performance significantly and preserves the decoding delay. The performance simulation and bit error rate and block error rate analysis are carried out on MATLAB software platform, and the function test and performance analysis of probabilistic LDPC decoder RTL code are carried out by Simulink and Modelsim co-simulation.
【學位授予單位】：電子科技大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TN911.22

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本文編號：1606990