基于FPGA的32點FFT算法的設計與實現(xiàn)
發(fā)布時間：2019-02-24 15:07
【摘要】：數(shù)字信號處理技術在當今社會的快速發(fā)展,得益于科學技術的快速前進，并且廣泛的應用在各種通信和計算機等領域，其中作為數(shù)字信號處理的基礎運算的離散傅里葉變換DFT在技術的運用中扮演者關鍵的角色，考慮到效率問題影響了離散傅里葉變換的應用，有人在二十世紀六十年代提出了快速傅里葉變換，也就是FFT，它有效地解決了前者的運算量龐大的問題，，并隨著科學技術的進步，它已成為DSP領域的重要技術。 FPGA現(xiàn)場可編程門陣列的出現(xiàn)使得數(shù)字信號處理的應用變得更加便捷，它基于PAL、GAL以及CPLD等技術的成熟而出現(xiàn)，它具有更靈活的編輯功能、很多的連接單元，非常適合于短周期的原型設計，相較傳統(tǒng)的成批量DSP和ASIC來說，更低的成本及更低的功耗使得人們更傾向選擇FPGA來作為開發(fā)的工具。這是因為FPGA的構成由硬件完成的，所以FPGA的基本構造較為簡單，一般情況下能夠包括較多的類似運算模塊，如此一來在實現(xiàn)同一功能的條件下，F(xiàn)PGA的處理運算速度會比普通的DSP芯片快很多。由于FFT較為固定的運算結構，由FPGA來實現(xiàn)是非常合適的，同時這種實現(xiàn)方式具備了設計要求的高效性和靈活性。 因此，本文選擇使用賽靈思Altera的芯片來實現(xiàn)32點的FFT時域抽取的順序處理器，這是一種通用的可以在FPGA上實現(xiàn)32點FFT變換的方法。整個FFT處理器采用了基-2時域抽取的基本算法原理，與此同時將流水線和并行的設計思想融入了FFT處理器的蝶形運算模塊的設計當中，同時處理器包含有地址產(chǎn)生模塊、時序控制模塊以及存儲模塊等其它模塊,這樣便組成了設計所要求的基-2FFT處理器。采用第三方的仿真軟件Modelsim對FFT模塊的前后設計流程進行了仿真Matlab軟件計并與算出精確地算法仿真結果,將它與設計的結果進行對比，驗證了該設計的準確性。仿真結果表明，設計的FFT處理器在滿足一定精度條件下，能夠順利地通過設計的基本指標。
[Abstract]:The rapid development of digital signal processing technology in today's society, thanks to the rapid progress of science and technology, and widely used in various communications and computer fields, The discrete Fourier transform (DFT), which is the basic operation of digital signal processing, plays a key role in the application of the technology. Considering the efficiency problem, the application of discrete Fourier transform is affected. In the sixties of the 20th century, some people put forward the fast Fourier transform, that is, FFT, which effectively solves the problem that the former has a huge amount of computation, and with the progress of science and technology, it has become an important technology in the field of DSP. The appearance of FPGA field programmable gate array makes the application of digital signal processing more convenient. It is based on the mature technology of PAL,GAL and CPLD. It has more flexible editing function and many connecting units. It is suitable for short period prototype design. Compared with traditional batch DSP and ASIC, lower cost and lower power consumption make people more inclined to choose FPGA as a development tool. This is because the composition of FPGA is made up of hardware, so the basic structure of FPGA is relatively simple. In general, it can include more similar computing modules, so that under the condition of realizing the same function, The processing speed of FPGA is much faster than that of ordinary DSP chips. Because of the fixed operation structure of FFT, it is very suitable to realize it by FPGA, and this implementation method has the high efficiency and flexibility of design requirement at the same time. Therefore, in this paper, we choose to use Altera chip to realize 32-point FFT time-domain decimation sequence processor, which is a universal method to realize 32-point FFT transform on FPGA. The whole FFT processor adopts the basic algorithm of base-2 time domain extraction. At the same time, the pipeline and parallel design ideas are integrated into the design of the butterfly operation module of the FFT processor, and the processor includes the address generation module. Timing control module, storage module and other modules, so as to form the design of the base-2FFT processor. The design flow of FFT module is simulated by the third-party simulation software Modelsim, and the simulation results of the algorithm are calculated and calculated accurately. The accuracy of the design is verified by comparing it with the results of the design. The simulation results show that the designed FFT processor can successfully pass the basic index of the design under certain precision conditions.
【學位授予單位】：西安電子科技大學
【學位級別】：碩士
【學位授予年份】：2014
【分類號】：TN791;TN911.72
本文編號：2429657
[Abstract]:The rapid development of digital signal processing technology in today's society, thanks to the rapid progress of science and technology, and widely used in various communications and computer fields, The discrete Fourier transform (DFT), which is the basic operation of digital signal processing, plays a key role in the application of the technology. Considering the efficiency problem, the application of discrete Fourier transform is affected. In the sixties of the 20th century, some people put forward the fast Fourier transform, that is, FFT, which effectively solves the problem that the former has a huge amount of computation, and with the progress of science and technology, it has become an important technology in the field of DSP. The appearance of FPGA field programmable gate array makes the application of digital signal processing more convenient. It is based on the mature technology of PAL,GAL and CPLD. It has more flexible editing function and many connecting units. It is suitable for short period prototype design. Compared with traditional batch DSP and ASIC, lower cost and lower power consumption make people more inclined to choose FPGA as a development tool. This is because the composition of FPGA is made up of hardware, so the basic structure of FPGA is relatively simple. In general, it can include more similar computing modules, so that under the condition of realizing the same function, The processing speed of FPGA is much faster than that of ordinary DSP chips. Because of the fixed operation structure of FFT, it is very suitable to realize it by FPGA, and this implementation method has the high efficiency and flexibility of design requirement at the same time. Therefore, in this paper, we choose to use Altera chip to realize 32-point FFT time-domain decimation sequence processor, which is a universal method to realize 32-point FFT transform on FPGA. The whole FFT processor adopts the basic algorithm of base-2 time domain extraction. At the same time, the pipeline and parallel design ideas are integrated into the design of the butterfly operation module of the FFT processor, and the processor includes the address generation module. Timing control module, storage module and other modules, so as to form the design of the base-2FFT processor. The design flow of FFT module is simulated by the third-party simulation software Modelsim, and the simulation results of the algorithm are calculated and calculated accurately. The accuracy of the design is verified by comparing it with the results of the design. The simulation results show that the designed FFT processor can successfully pass the basic index of the design under certain precision conditions.
【學位授予單位】：西安電子科技大學
【學位級別】：碩士
【學位授予年份】：2014
【分類號】：TN791;TN911.72
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