后向投影算法并行計算系統(tǒng)設(shè)計
發(fā)布時間：2019-02-21 15:47
【摘要】：后向投影(back projection, BP)雷達(dá)成像算法是一種基于時域處理的雷達(dá)成像算法,具有很好的魯棒性,適用于載機任意運動和非均勻孔徑合成孔徑雷達(dá)成像。盡管BP算法可以不加任何近似的應(yīng)用在SAR成像中,但是它的計算效率很低,運算量與回波脈沖數(shù)和目標(biāo)圖像像素點數(shù)成正比,所以在高分辨率成像應(yīng)用中運算量非常大,運算時間很長,所以如何提高算法運算效率成為當(dāng)前亟待解決的問題。本文從并行化的角度出發(fā)對算法進行優(yōu)化,在充分分析算法并發(fā)特征的基礎(chǔ)上,提出三種并行優(yōu)化方法,并設(shè)計了基于NoC多核的軟硬件成像系統(tǒng),有效提高了算法運算效率。根據(jù)FPGA實驗結(jié)果,本文還提出兩種系統(tǒng)實時成像方案,為該算法的實際應(yīng)用提供兩種途徑。為加快多核成像系統(tǒng)的設(shè)計效率,本文首先采用C++和SystemC建立系統(tǒng)的C模型和TLM模型,從宏觀上統(tǒng)一規(guī)劃整個系統(tǒng)架構(gòu),對系統(tǒng)軟硬件進行了合理劃分,在早期對軟硬件進行協(xié)同驗證,縮短了系統(tǒng)設(shè)計周期。在系統(tǒng)模型的基礎(chǔ)上,基于NoC和多核架構(gòu),設(shè)計相應(yīng)的硬件和系統(tǒng)軟件。并將算法中運算量最大而又具有良好并發(fā)性的反投影運算部分封裝成硬件加速核,通過集成多個加速核,進一步提高算法運算效率。系統(tǒng)選用ARM處理器作為子系統(tǒng)的主控核,設(shè)計相應(yīng)的并行軟件,最終實現(xiàn)BP算法的高性能計算系統(tǒng)。在FPGA上對所設(shè)計的系統(tǒng)進行驗證。對于8K*4K大小的目標(biāo)圖像,在PC上不經(jīng)過加速的成像時間為5小時23分鐘,而本系統(tǒng)的成像時間只需要5分10秒,加速比高達(dá)65倍,驗證了所設(shè)計系統(tǒng)的有效性。最后,針對8K*4K大小目標(biāo)圖像在FPGA上的實驗結(jié)果仍然無法滿足實時成像應(yīng)用需求這一問題,本文給出分析,并提出兩種有效解決方案,為系統(tǒng)實際應(yīng)用提供了有效解決途徑。
[Abstract]:The backward projection (back projection, BP) radar imaging algorithm is a kind of radar imaging algorithm based on time domain processing. It has good robustness and is suitable for airborne arbitrary motion and non-uniform aperture synthetic aperture radar imaging. Although the BP algorithm can be used in SAR imaging without any approximation, its computational efficiency is very low. The computation quantity is in direct proportion to the number of echo pulses and the number of pixels in the target image, so it is very large in the application of high resolution imaging. The operation time is very long, so how to improve the efficiency of the algorithm becomes an urgent problem. In this paper, the algorithm is optimized from the point of view of parallelization. On the basis of fully analyzing the concurrency characteristics of the algorithm, three parallel optimization methods are proposed, and the hardware and software imaging system based on NoC multi-core is designed, which effectively improves the efficiency of the algorithm. Based on the experimental results of FPGA, two real time imaging schemes are proposed, which provide two approaches for the practical application of the algorithm. In order to accelerate the design efficiency of the multi-core imaging system, the C model and the TLM model of the system are established by C and SystemC firstly, and the whole system architecture is unified from the macro view, and the software and hardware of the system are divided reasonably. In the early stage of hardware and software co-verification, the system design cycle is shortened. Based on the system model, the corresponding hardware and software are designed based on NoC and multi-core architecture. The backprojection operation which has the largest computation and good concurrency in the algorithm is encapsulated into the hardware accelerating kernel. The efficiency of the algorithm is further improved by integrating several accelerating cores. The system chooses ARM processor as the main control core of the subsystem, designs the corresponding parallel software, and finally realizes the high performance computing system of the BP algorithm. The designed system is verified on FPGA. For the target image with the size of 8K*4K, the imaging time without acceleration on the PC is 5 hours and 23 minutes, but the imaging time of the system is only 5 minutes and 10 seconds, and the acceleration ratio is as high as 65 times. The validity of the designed system is verified. Finally, aiming at the problem that the experimental results of 8K*4K size target images on FPGA still can not meet the requirements of real-time imaging applications, this paper gives an analysis and puts forward two effective solutions, which provide an effective solution for the practical application of the system.
【學(xué)位授予單位】：南京大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TN957.52
本文編號：2427640
[Abstract]:The backward projection (back projection, BP) radar imaging algorithm is a kind of radar imaging algorithm based on time domain processing. It has good robustness and is suitable for airborne arbitrary motion and non-uniform aperture synthetic aperture radar imaging. Although the BP algorithm can be used in SAR imaging without any approximation, its computational efficiency is very low. The computation quantity is in direct proportion to the number of echo pulses and the number of pixels in the target image, so it is very large in the application of high resolution imaging. The operation time is very long, so how to improve the efficiency of the algorithm becomes an urgent problem. In this paper, the algorithm is optimized from the point of view of parallelization. On the basis of fully analyzing the concurrency characteristics of the algorithm, three parallel optimization methods are proposed, and the hardware and software imaging system based on NoC multi-core is designed, which effectively improves the efficiency of the algorithm. Based on the experimental results of FPGA, two real time imaging schemes are proposed, which provide two approaches for the practical application of the algorithm. In order to accelerate the design efficiency of the multi-core imaging system, the C model and the TLM model of the system are established by C and SystemC firstly, and the whole system architecture is unified from the macro view, and the software and hardware of the system are divided reasonably. In the early stage of hardware and software co-verification, the system design cycle is shortened. Based on the system model, the corresponding hardware and software are designed based on NoC and multi-core architecture. The backprojection operation which has the largest computation and good concurrency in the algorithm is encapsulated into the hardware accelerating kernel. The efficiency of the algorithm is further improved by integrating several accelerating cores. The system chooses ARM processor as the main control core of the subsystem, designs the corresponding parallel software, and finally realizes the high performance computing system of the BP algorithm. The designed system is verified on FPGA. For the target image with the size of 8K*4K, the imaging time without acceleration on the PC is 5 hours and 23 minutes, but the imaging time of the system is only 5 minutes and 10 seconds, and the acceleration ratio is as high as 65 times. The validity of the designed system is verified. Finally, aiming at the problem that the experimental results of 8K*4K size target images on FPGA still can not meet the requirements of real-time imaging applications, this paper gives an analysis and puts forward two effective solutions, which provide an effective solution for the practical application of the system.
【學(xué)位授予單位】：南京大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TN957.52
【參考文獻】
相關(guān)期刊論文 前7條
1 韓正飛;李勁松;潘紅兵;李麗;沙金;何書專;;基于FPGA的浮點向量協(xié)處理器設(shè)計[J];計算機工程;2012年05期
2 黃曉林;潘紅兵;易偉;楊虎;凌夢;黃辰;何書專;李麗;;基于多FPGA的NoC多核處理器驗證平臺設(shè)計[J];計算機工程與設(shè)計;2012年01期
3 盧風(fēng)順;宋君強;銀福康;張理論;;CPU/GPU協(xié)同并行計算研究綜述[J];計算機科學(xué);2011年03期
4 何晶;陳家新;黎蔚;;基于GPU的實時光線投射算法[J];計算機工程與應(yīng)用;2008年09期
5 沈緒榜;劉澤響;王茹;;計算機體系結(jié)構(gòu)的統(tǒng)一模型[J];計算機學(xué)報;2007年05期
6 吳恩華;圖形處理器用于通用計算的技術(shù)、現(xiàn)狀及其挑戰(zhàn)[J];軟件學(xué)報;2004年10期
7 吳恩華,柳有權(quán);基于圖形處理器(GPU)的通用計算[J];計算機輔助設(shè)計與圖形學(xué)學(xué)報;2004年05期
相關(guān)博士學(xué)位論文 前3條
1 許牧;可重構(gòu)眾核流處理器體系結(jié)構(gòu)關(guān)鍵技術(shù)研究[D];中國科學(xué)技術(shù)大學(xué);2012年
2 嚴(yán)明;面向領(lǐng)域應(yīng)用的異構(gòu)多核SoC系統(tǒng)結(jié)構(gòu)設(shè)計與優(yōu)化[D];國防科學(xué)技術(shù)大學(xué);2011年
3 馬安國;高效能GPGPU體系結(jié)構(gòu)關(guān)鍵技術(shù)研究[D];國防科學(xué)技術(shù)大學(xué);2011年
相關(guān)碩士學(xué)位論文 前1條
1 張帆;基于GPU加速的醫(yī)學(xué)圖像3D實時繪制技術(shù)[D];電子科技大學(xué);2009年
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