【摘要】：雷達(dá)信號(hào)處理器是雷達(dá)系統(tǒng)的關(guān)鍵組成,現(xiàn)代戰(zhàn)場(chǎng)上其面對(duì)的環(huán)境越來(lái)越復(fù)雜,面對(duì)的挑戰(zhàn)越來(lái)越嚴(yán)峻,對(duì)雷達(dá)信號(hào)處理器的要求不僅是實(shí)時(shí)性,更要求其具有抗干擾、抗輻射等特性,數(shù)字化的陣列雷達(dá)信號(hào)處理因其具有諸多優(yōu)秀的特性而成為一種發(fā)展的趨勢(shì)。數(shù)字下變頻(DDC)將模數(shù)轉(zhuǎn)換器(ADC)采樣后的數(shù)據(jù)混頻到零頻,濾除無(wú)用信息,并進(jìn)行抽取操作,便于后級(jí)進(jìn)行數(shù)字信號(hào)處理(DSP)。數(shù)字波束形成(DBF)能夠?qū)﹃嚵刑炀�接收的信息充分利用,通過(guò)加權(quán)運(yùn)算,產(chǎn)生特定指向的波束,可以進(jìn)行抑制干擾、波束掃描等操作。DDC和DBF是數(shù)字化陣列雷達(dá)信號(hào)處理器的關(guān)鍵單元,本文分別對(duì)其設(shè)計(jì)與實(shí)現(xiàn)進(jìn)行了研究,主要工作有:1.根據(jù)雷達(dá)信號(hào)處理器的靈活性要求,運(yùn)用有限狀態(tài)機(jī)技術(shù)設(shè)計(jì)了可配置DDC。該設(shè)計(jì)可以實(shí)現(xiàn)濾波階數(shù)、濾波系數(shù)和抽取倍數(shù)的可配置,并運(yùn)用多通道FIR結(jié)構(gòu)進(jìn)行時(shí)分復(fù)用。對(duì)該DDC電路進(jìn)行MATLAB和Modelsim聯(lián)合仿真,并使用FPGA平臺(tái)進(jìn)行原型驗(yàn)證�；赟MIC 0.13μm的標(biāo)準(zhǔn)工藝庫(kù)完成了邏輯綜合、靜態(tài)時(shí)序分析和形式驗(yàn)證,頻率可達(dá)166MHz,面積為609035μm2。2.根據(jù)雷達(dá)信號(hào)處理器的低成本要求,設(shè)計(jì)了低成本DDC。將混頻、濾波和抽取三個(gè)模塊合并,提出了多相混頻抽取濾波器,并運(yùn)用多通道FIR結(jié)構(gòu)進(jìn)行時(shí)分復(fù)用,減小了面積,降低了成本。對(duì)該DDC電路進(jìn)行MATLAB和Modelsim聯(lián)合仿真,并使用FPGA平臺(tái)進(jìn)行原型驗(yàn)證。基于SMIC 0.13μm的標(biāo)準(zhǔn)工藝庫(kù)完成了邏輯綜合、靜態(tài)時(shí)序分析和形式驗(yàn)證,頻率可達(dá)166MHz,面積為177533μm2。3.根據(jù)雷達(dá)信號(hào)處理器的高速率要求,設(shè)計(jì)了高速率DDC。運(yùn)用多相濾波結(jié)構(gòu)對(duì)輸入數(shù)據(jù)劃分通道,實(shí)現(xiàn)了對(duì)高速率輸入數(shù)據(jù)的下變頻處理。對(duì)該DDC電路進(jìn)行MATLAB和Modelsim聯(lián)合仿真,并使用FPGA平臺(tái)進(jìn)行原型驗(yàn)證�；赟MIC0.13μm的標(biāo)準(zhǔn)工藝庫(kù)完成了邏輯綜合、靜態(tài)時(shí)序分析和形式驗(yàn)證,頻率可達(dá)1GHz,面積為376454μm2。4.根據(jù)DBF原理,對(duì)8陣元DBF進(jìn)行了MATLAB建模。并運(yùn)用最小均方差準(zhǔn)則、最大信噪比準(zhǔn)則和線性約束最小方差準(zhǔn)則進(jìn)行了8陣元自適應(yīng)數(shù)字波束形成(ADBF)的MATLAB建模。對(duì)8陣元DBF進(jìn)行電路設(shè)計(jì),基于Virtex 4器件進(jìn)行功能驗(yàn)證,綜合后最高頻率為270.53MHz。
[Abstract]:Radar signal processor is the key component of radar system. The environment it faces on the modern battlefield is becoming more and more complex and the challenge is becoming more and more severe. The requirement of radar signal processor is not only real-time, but also anti-jamming. The digital array radar signal processing has become a development trend because of its many excellent characteristics. Digital down conversion (DDC) (DDC) mixes the data sampled by (ADC) to zero frequency, filter out useless information, and decimate, which is convenient for digital signal processing (DSP). Digital beamforming (DBF) can make full use of the information received by the array antenna, and through weighting operation, it can produce a specific direction beam, which can suppress interference. Beam scanning and other operations. DDC and DBF are the key units of digital array radar signal processor. The design and implementation of them are studied in this paper. The main work is as follows: 1. According to the flexibility requirement of radar signal processor, a configurable DDC. is designed using finite state machine technology. This design can realize the configuration of filter order, filter coefficient and decimation multiple, and use multi-channel FIR structure for time division multiplexing. The DDC circuit is simulated by MATLAB and Modelsim, and the prototype is verified by FPGA platform. The standard process library based on SMIC 0.13 渭 m has completed logic synthesis, static timing analysis and formal verification. The frequency can reach 166 MHz and the area is 609035 渭 m 2.2. According to the low cost requirement of radar signal processor, a low cost DDC. is designed. Mixing, filtering and decimating modules are combined, and a multiphase mixing decimation filter is proposed. The multichannel FIR structure is used for time division multiplexing, which reduces the area and cost. The DDC circuit is simulated by MATLAB and Modelsim, and the prototype is verified by FPGA platform. The standard process library based on SMIC 0.13 渭 m has completed logic synthesis, static timing analysis and formal verification. The frequency can reach 166MHz and the area is 177533 渭 m 2.3. According to the high rate requirement of radar signal processor, a high rate DDC. is designed. The input data is divided into channels by using polyphase filter structure, and the downconversion processing of high rate input data is realized. The DDC circuit is simulated by MATLAB and Modelsim, and the prototype is verified by FPGA platform. The standard process library based on SMIC0.13 渭 m has completed logic synthesis, static timing analysis and formal verification. The frequency can reach 1 GHz and the area is 376454 渭 m 2.4. According to the principle of DBF, the 8 matrix DBF is modeled by MATLAB. The MATLAB model of adaptive digital beamforming (ADBF) based on 8-element adaptive digital beamforming is established by using the minimum mean square error criterion, the maximum signal-to-noise ratio criterion and the linear constraint minimum variance criterion. The circuit design of 8 array element DBF is carried out, and the function is verified based on Virtex 4 device. The highest frequency of synthesis is 270.53 MHz.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類號(hào)】：TN957.51

【參考文獻(xiàn)】

相關(guān)碩士學(xué)位論文 前1條

1 倪丁華;分塊并行DBF算法及其實(shí)現(xiàn)[D];南京理工大學(xué);2009年

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本文編號(hào)：2403827