相控陣雷達波束控制技術研究
發(fā)布時間：2018-12-13 07:20
【摘要】：波控系統(tǒng)是有源相控陣雷達的重要組成部分,主要作用是形成特定指向、低旁瓣、能規(guī)避特定干擾的波束信號。本論文根據某型相控陣雷達項目實際需求,首先研究和仿真了如何形成規(guī)避特定波束指向干擾信號的零點調向算法,然后設計并且完成了一個能控制T/R模塊幅度和相位參數的波束控制電路系統(tǒng),最后針對該電路系統(tǒng)FPGA外圍特點,將零點調向算法利用MODESIM進行具體功能化實現。本課題提出了一種新的波控機硬件實現方法,該波控機具有運算能力強大、數據吞吐能力強的特點;零點調向算法的工程化設計方法具有實現簡便、通用性好的特點。算法仿真部分首先研究了均勻線陣的數學模型和波束形成的零點約束條件,利用最小二乘法和拉格朗日算子進行最優(yōu)系數求解,得到了零點調向系數求解公式。此外,利用仿真分析了零階約束條件對波束形成的影響,為后續(xù)工程化實現打下基礎。算法FPGA實現部分首先對比了零點調向的幾種常見方法,利用課題算法仿真結果設計出一種基于FPGA實現的零點調向方法。為實現和浮點DSP之間的無縫連接,所有數據采用IEEE754標準浮點單精度格式,實現主要涉及了向量和矩陣的乘加運算。底層利用IP核實現核心算法,采用狀態(tài)機實現時序控制,整個過程利用MODESIM與QUARTUS II軟件聯合完成。波控電路系統(tǒng)實現部分首先分析和研究了經典的波控機結構組成,然后根據具體項目要求設計了DSP與FPGA混合架構的波控系統(tǒng),最后經過焊接、調試后用于實際工程項目中。波控機核心運算單元采用ADI公司的TS101和ALTERA公司的EP2S90,它們構成的運算核心具有強大的數據處理能力。波控電路系統(tǒng)外圍接口豐富,最多能控制8×8陣元的T/R模塊,能進行網絡和串口的上位機控制,有超過16個IO命令擴展接口。波控電路系統(tǒng)數據存儲能力強大,有超過2G×8位的FLASH存儲器可用于標校數據存儲,以及512K×32位乒乓無縫RAM實時存儲器。
[Abstract]:Wave control system is an important part of active phased array radar. The main function is to form a specific direction, low sidelobe, and avoid the special interference of the beam signal. According to the actual requirements of a phased array radar project, this paper first studies and simulates how to form a zero-point direction modulation algorithm to avoid the interference signal of a specific beam. Then, a beam-beam control circuit system which can control the amplitude and phase parameters of the T / R module is designed and completed. Finally, according to the peripheral characteristics of the circuit system FPGA, the zeroing algorithm is realized by using MODESIM. In this paper, a new method of realizing the hardware of the wave controller is presented, which has the characteristics of powerful operation ability and strong data throughput, and the engineering design method of the zero direction adjustment algorithm has the characteristics of simple realization and good generality. In the simulation part of the algorithm, the mathematical model of uniform linear array and the zero point constraint condition of beamforming are studied. The optimal coefficient is solved by using least square method and Lagrange operator, and the formula of zero point direction adjustment coefficient is obtained. In addition, the effect of zero order constraint on beamforming is analyzed by simulation. In the part of FPGA implementation, several common methods of zero direction adjustment are compared, and a zero direction adjustment method based on FPGA is designed by using the simulation results of the algorithm. In order to realize the seamless connection between DSP and floating-point, all the data adopt IEEE754 standard floating-point single-precision format, which mainly involves the multiplication and addition of vectors and matrices. In the bottom layer, the core algorithm is realized by IP core, the timing control is realized by state machine, and the whole process is accomplished by MODESIM and QUARTUS II software. In the realization part of the wave control circuit system, the structure of the classical wave control machine is analyzed and studied firstly, and then the wave control system based on the DSP and FPGA hybrid architecture is designed according to the specific project requirements. After welding and debugging, the system is used in the actual engineering project. The core operation unit of the wave control machine is composed of TS101 of ADI Company and EP2S90, of ALTERA Company, which have powerful data processing ability. The wave control circuit system has abundant peripheral interfaces and can control 8 脳 8 array elements of the T / R module at most. It can control the upper computer of network and serial port. There are more than 16 IO command extension interfaces. The data storage ability of the wave control circuit system is very powerful. The FLASH memory with more than 2G 脳 8 bits can be used for calibrating data storage and 512K 脳 32-bit ping-pong seamless RAM real-time memory.
【學位授予單位】：哈爾濱工業(yè)大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN958.92
本文編號：2376140
[Abstract]:Wave control system is an important part of active phased array radar. The main function is to form a specific direction, low sidelobe, and avoid the special interference of the beam signal. According to the actual requirements of a phased array radar project, this paper first studies and simulates how to form a zero-point direction modulation algorithm to avoid the interference signal of a specific beam. Then, a beam-beam control circuit system which can control the amplitude and phase parameters of the T / R module is designed and completed. Finally, according to the peripheral characteristics of the circuit system FPGA, the zeroing algorithm is realized by using MODESIM. In this paper, a new method of realizing the hardware of the wave controller is presented, which has the characteristics of powerful operation ability and strong data throughput, and the engineering design method of the zero direction adjustment algorithm has the characteristics of simple realization and good generality. In the simulation part of the algorithm, the mathematical model of uniform linear array and the zero point constraint condition of beamforming are studied. The optimal coefficient is solved by using least square method and Lagrange operator, and the formula of zero point direction adjustment coefficient is obtained. In addition, the effect of zero order constraint on beamforming is analyzed by simulation. In the part of FPGA implementation, several common methods of zero direction adjustment are compared, and a zero direction adjustment method based on FPGA is designed by using the simulation results of the algorithm. In order to realize the seamless connection between DSP and floating-point, all the data adopt IEEE754 standard floating-point single-precision format, which mainly involves the multiplication and addition of vectors and matrices. In the bottom layer, the core algorithm is realized by IP core, the timing control is realized by state machine, and the whole process is accomplished by MODESIM and QUARTUS II software. In the realization part of the wave control circuit system, the structure of the classical wave control machine is analyzed and studied firstly, and then the wave control system based on the DSP and FPGA hybrid architecture is designed according to the specific project requirements. After welding and debugging, the system is used in the actual engineering project. The core operation unit of the wave control machine is composed of TS101 of ADI Company and EP2S90, of ALTERA Company, which have powerful data processing ability. The wave control circuit system has abundant peripheral interfaces and can control 8 脳 8 array elements of the T / R module at most. It can control the upper computer of network and serial port. There are more than 16 IO command extension interfaces. The data storage ability of the wave control circuit system is very powerful. The FLASH memory with more than 2G 脳 8 bits can be used for calibrating data storage and 512K 脳 32-bit ping-pong seamless RAM real-time memory.
【學位授予單位】：哈爾濱工業(yè)大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN958.92
【參考文獻】
相關期刊論文 前10條
1 焦淑紅;焦壯;;基于多核DSP的以太網通信接口設計[J];電子科技;2015年09期
2 賈芳;鄭丹;;基于FPGA高精度時間間隔系統(tǒng)設計與實現[J];自動化與儀器儀表;2015年02期
3 張慧;何常德;苗靜;李玉平;張文棟;薛晨陽;;一種基于MATLAB的CMUT陣列設計與成像仿真方法[J];傳感技術學報;2014年04期
4 車明陽;于林韜;朱建東;;淺談基于FPGA的相控陣雷達波束控制系統(tǒng)設計[J];信息通信;2013年08期
5 蔡巍;張曉鋒;喬鳴忠;何必;朱鵬;陳雷;;基于DSP+FPGA控制架構的矩陣變換器設計[J];船電技術;2013年09期
6 杜慧敏;馬超;;一種快速浮點乘法單元的設計與實現[J];西安郵電大學學報;2013年01期
7 夏勇;張浩;李曉娟;尤路;;二次雷達波束控制系統(tǒng)設計[J];信息與電子工程;2012年03期
8 劉賢明;吳學伍;袁魏華;;基于TS101的雷達信號處理板設計[J];桂林航天工業(yè)高等�？茖W校學報;2012年01期
9 羅敏;;多功能相控陣雷達發(fā)展現狀及趨勢[J];現代雷達;2011年09期
10 �；哿�;馬莉;張健;;一種基于FPGA的雷達波束控制系統(tǒng)設計[J];現代電子技術;2010年08期
，本文編號：2376140
本文鏈接：http://www.sikaile.net/kejilunwen/wltx/2376140.html
最近更新
教材專著
