高速串行收發(fā)系統(tǒng)關(guān)鍵模塊的研究
發(fā)布時(shí)間：2018-12-09 12:42
【摘要】：高速串行數(shù)據(jù)傳輸要求數(shù)據(jù)信號(hào)在傳輸線上以單比特形式連續(xù)傳送,而提高單個(gè)數(shù)據(jù)lane傳輸帶寬的方法是盡量提高時(shí)鐘頻率,但是,增大時(shí)鐘頻率會(huì)引起嚴(yán)重的碼間干擾,高頻分量被嚴(yán)重?fù)p耗,而且傳輸數(shù)據(jù)中長連續(xù)的0或1會(huì)使信號(hào)下一刻反向跳變值不足,傳輸線路直流平衡性變差,接收端鎖定時(shí)鐘變的更加困難,這都將降低數(shù)據(jù)傳輸率。本文主要做了如下工作:1.在對(duì)數(shù)據(jù)流經(jīng)的發(fā)送端、傳輸線和接收端的各個(gè)模塊詳細(xì)分析的基礎(chǔ)上,提出了發(fā)送端電路設(shè)計(jì)架構(gòu),劃分?jǐn)?shù)字電路和模擬電路部分,定義設(shè)計(jì)整體和各模塊的端口信號(hào),性能指標(biāo),各采用數(shù)字電路和模擬電路設(shè)計(jì)方法實(shí)現(xiàn)。2.針對(duì)傳輸線直流平衡性和時(shí)鐘相位差問題,采用數(shù)字電路半定制設(shè)計(jì)方法實(shí)現(xiàn)了等時(shí)同步FIFO、8B/10B編碼器和串化器,其中編碼過程分解為3B/4B和5B/6B編碼,并設(shè)置有效數(shù)據(jù)字符和控制字符選擇信號(hào),以及運(yùn)行不一致性指示信號(hào),有效地打亂傳輸數(shù)據(jù)中長連續(xù)0或1,為接收端鎖定時(shí)鐘提供足夠的信號(hào)躍變;3.針對(duì)碼間干擾問題,設(shè)計(jì)具有預(yù)加重功能的驅(qū)動(dòng)電路,補(bǔ)償高頻分量在傳輸線上的損耗。在傳統(tǒng)LVDS驅(qū)動(dòng)電路基礎(chǔ)上,(1)添加并聯(lián)分流組件,減小總電阻,增大負(fù)載電流;(2)添加第二電流源,增加負(fù)載電流值;(3)并聯(lián)兩個(gè)CML電路,并將其中一個(gè)輸出延遲一定時(shí)間實(shí)現(xiàn)加重信號(hào)。半定制設(shè)計(jì)方法實(shí)現(xiàn)數(shù)字電路部分,采用Verilog HDL描述其功能,用Modelsim做功能仿真,并在130nm CMOS工藝下,DC軟件綜合映射其門級(jí)網(wǎng)表,分析導(dǎo)出的面積、功耗、時(shí)序等報(bào)告。LVDS和CML驅(qū)動(dòng)電路本設(shè)計(jì)采用Virtuoso軟件在130nm CMOS工藝下,實(shí)現(xiàn)電路結(jié)構(gòu),在Hspice軟件模擬仿真達(dá)到3.125Gbps傳輸帶寬,通過添加合適的負(fù)載電容,調(diào)整mos管的寬長比,減小毛刺,達(dá)到最優(yōu)效果。
[Abstract]:High speed serial data transmission requires the data signal to be transmitted continuously in the form of single bit on the transmission line. The method of increasing the transmission bandwidth of single data lane is to increase the clock frequency as far as possible, but increasing the clock frequency will cause serious inter-symbol interference. The high frequency component is seriously lost, and the long and continuous 0 or 1 in the transmission data will make the reverse jump value of the signal at the next moment insufficient, the DC balance of the transmission line will become worse, and the lock clock of the receiver will become more difficult, which will reduce the data transmission rate. The main work of this paper is as follows: 1. On the basis of the detailed analysis of each module of the transmitting end, transmission line and receiving end of the data flow, this paper puts forward the design architecture of the transmitter circuit, divides the digital circuit and the analog circuit, and defines the whole design and the port signal of each module. Performance index, each using digital circuit and analog circuit design method to achieve. 2. In order to solve the problem of DC balance and clock phase difference of transmission line, an isochronous synchronous FIFO,8B/10B encoder and serializer is implemented by using digital circuit semi-custom design method, in which the encoding process is decomposed into 3B/4B and 5B/6B codes. Effective data characters and control character selection signals are set, and inconsistency indication signals are run to effectively disrupt the length of 0 or 1 in the transmitted data, so as to provide sufficient signal jump for the lock clock at the receiving end. 3. To solve the problem of inter-symbol interference (ISI), a driving circuit with preweighting function is designed to compensate the loss of high-frequency components on transmission lines. On the basis of the traditional LVDS drive circuit, (1) adding shunt component to reduce the total resistance and increase the load current, (2) adding the second current source to increase the load current value; (3) parallel two CML circuits, and delay one of them to realize the accentuation signal. The semi-custom design method is used to realize the digital circuit. Verilog HDL is used to describe the function, and Modelsim is used to simulate the function. Under the 130nm CMOS process, the DC software synthetically maps its gate network table, and analyzes the area and power consumption derived. The design of LVDS and CML driver circuit uses Virtuoso software under 130nm CMOS technology to realize the circuit structure, in the Hspice software simulation to achieve 3.125Gbps transmission bandwidth, through the addition of appropriate load capacitance, adjust the mos tube width ratio, Reduce the burr to achieve the best effect.
【學(xué)位授予單位】：國防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類號(hào)】：TN919.3
本文編號(hào)：2369380
[Abstract]:High speed serial data transmission requires the data signal to be transmitted continuously in the form of single bit on the transmission line. The method of increasing the transmission bandwidth of single data lane is to increase the clock frequency as far as possible, but increasing the clock frequency will cause serious inter-symbol interference. The high frequency component is seriously lost, and the long and continuous 0 or 1 in the transmission data will make the reverse jump value of the signal at the next moment insufficient, the DC balance of the transmission line will become worse, and the lock clock of the receiver will become more difficult, which will reduce the data transmission rate. The main work of this paper is as follows: 1. On the basis of the detailed analysis of each module of the transmitting end, transmission line and receiving end of the data flow, this paper puts forward the design architecture of the transmitter circuit, divides the digital circuit and the analog circuit, and defines the whole design and the port signal of each module. Performance index, each using digital circuit and analog circuit design method to achieve. 2. In order to solve the problem of DC balance and clock phase difference of transmission line, an isochronous synchronous FIFO,8B/10B encoder and serializer is implemented by using digital circuit semi-custom design method, in which the encoding process is decomposed into 3B/4B and 5B/6B codes. Effective data characters and control character selection signals are set, and inconsistency indication signals are run to effectively disrupt the length of 0 or 1 in the transmitted data, so as to provide sufficient signal jump for the lock clock at the receiving end. 3. To solve the problem of inter-symbol interference (ISI), a driving circuit with preweighting function is designed to compensate the loss of high-frequency components on transmission lines. On the basis of the traditional LVDS drive circuit, (1) adding shunt component to reduce the total resistance and increase the load current, (2) adding the second current source to increase the load current value; (3) parallel two CML circuits, and delay one of them to realize the accentuation signal. The semi-custom design method is used to realize the digital circuit. Verilog HDL is used to describe the function, and Modelsim is used to simulate the function. Under the 130nm CMOS process, the DC software synthetically maps its gate network table, and analyzes the area and power consumption derived. The design of LVDS and CML driver circuit uses Virtuoso software under 130nm CMOS technology to realize the circuit structure, in the Hspice software simulation to achieve 3.125Gbps transmission bandwidth, through the addition of appropriate load capacitance, adjust the mos tube width ratio, Reduce the burr to achieve the best effect.
【學(xué)位授予單位】：國防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2014
【分類號(hào)】：TN919.3
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