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超短波無線通信軟件無線電數(shù)字平臺的設(shè)計與實現(xiàn)

發(fā)布時間:2018-11-15 19:29
【摘要】:理想的軟件無線電架構(gòu)由可重新配置的數(shù)字無線電、植入阻抗合成器的軟件可調(diào)無線電和軟件可調(diào)天線系統(tǒng)三個主要單元組成。軟件無線電最初被認為是在協(xié)同工作、廣義范圍內(nèi)無線互通、多模式、多標準等方面具有廣闊前景的無線電通信系統(tǒng)應用解決方案,是未來無線通信和全球電信技術(shù)發(fā)展的新方向。本方案的目的是實現(xiàn)一個通用化、開放化、模塊化架構(gòu)的軟件無線電硬件平臺,由于硬件如A/D,D/A轉(zhuǎn)換和DSP和FPGA等處理器性能的限制,我們無法采用理想軟件無線電模型的架構(gòu)。基于當前集成電路技術(shù)和無線通信技術(shù)的發(fā)展,我們采用了中頻數(shù)字化的系統(tǒng)框架,即先通過射頻前端將射頻信號轉(zhuǎn)換至中頻,數(shù)字平臺實現(xiàn)中頻和基帶之間的轉(zhuǎn)換,然后再由基帶單元進行信號處理。軟件設(shè)計上采用基于SCA架構(gòu)的統(tǒng)一處理體系,實現(xiàn)組件化、模塊化實現(xiàn)方式,方便裁剪和異構(gòu),和數(shù)字硬件平臺一起構(gòu)建了實用的軟件無線電通信平臺。本方案實現(xiàn)的軟件無線電架構(gòu),核心單元是一個基帶信號數(shù)字處理硬件平臺,主要設(shè)計內(nèi)容有:軟件無線電理論的研究、數(shù)字平臺設(shè)計與實現(xiàn)、總體方案的論證編寫、核心處理器的選擇、電路原理圖設(shè)計、PCB實現(xiàn)、數(shù)字平臺的調(diào)試與驗證,硬件底層驅(qū)動程序的編寫。概述了軟件無線電的發(fā)展歷程及現(xiàn)狀,闡述了信號采樣理論與多速率信號處理理論等數(shù)字信號處理相關(guān)理論基礎(chǔ)。本方案采用DSP+FPGA+GPP的框架作為本次設(shè)計指導思想。整個硬件平臺分為黑邊基帶單元和紅邊業(yè)務接口單元兩部分。DSP基帶板的核心芯片采用TI的TMS320C6416,FPGA芯片采用的是Xilinx公司VirtexII系列FPGA中的XC2V3000。設(shè)計使用Cadence 15.5完成了電路原理圖和高速PCB設(shè)計。在理論分析的基礎(chǔ)上,結(jié)合基帶數(shù)字電路技術(shù)發(fā)展,最終設(shè)計實現(xiàn)了一款通用的軟件無線電架構(gòu)的數(shù)字硬件平臺,通過GPP+FPGA+DSP的框架架構(gòu)實現(xiàn)了基帶數(shù)字電路,最后通過單板調(diào)試和整機功能測試,正確實現(xiàn)了數(shù)字平臺的設(shè)計功能。
[Abstract]:The ideal software radio architecture consists of three main units: a reconfigurable digital radio, a software tunable radio embedded in an impedance synthesizer and a software tunable antenna system. Software radio was originally considered as a promising solution for wireless communication systems with broad prospects for collaborative work, wireless interworking in a broad sense, multi-mode, multi-standard, and so on. Is the future wireless communication and the global telecommunication technology development new direction. The purpose of this scheme is to implement a software radio hardware platform with a general, open and modular architecture, which is limited by the performance of hardware such as A / D / A conversion and DSP and FPGA processors. We cannot adopt the architecture of the ideal software radio model. Based on the development of current integrated circuit technology and wireless communication technology, we adopt the system framework of if digitization, that is, the RF signal is converted to if through RF front-end, and the digital platform realizes the conversion between if and baseband. The signal is then processed by the baseband unit. In software design, a unified processing system based on SCA architecture is adopted to realize componentization and modularization, which is convenient for cutting and heterogeneous, and a practical software radio communication platform is constructed together with the digital hardware platform. The core unit of the software radio architecture is a hardware platform for baseband signal digital processing. The main design contents are: the research of software radio theory, the design and implementation of digital platform, the argumentation and compilation of the overall scheme. Core processor selection, circuit schematic design, PCB implementation, digital platform debugging and verification, hardware bottom driver programming. In this paper, the development and present situation of software radio are summarized, and the related theories of digital signal processing, such as signal sampling theory and multi-rate signal processing theory, are expounded. This project adopts the framework of DSP FPGA GPP as the guiding principle of this design. The whole hardware platform is divided into two parts: black edge baseband unit and red edge service interface unit. The core chip of DSP baseband board is TI's TMS320C6416,FPGA chip, which is the XC2V3000. of VirtexII series FPGA of Xilinx Company. The circuit schematic diagram and high speed PCB are designed with Cadence 15. 5. On the basis of theoretical analysis, combined with the development of baseband digital circuit technology, a digital hardware platform of a general software radio architecture is designed and implemented. The baseband digital circuit is realized through the framework of GPP FPGA DSP. Finally, the design function of the digital platform is realized correctly through the debugging of the single board and the testing of the function of the whole machine.
【學位授予單位】:電子科技大學
【學位級別】:碩士
【學位授予年份】:2014
【分類號】:TN925

【參考文獻】

相關(guān)期刊論文 前1條

1 沙燕萍,皇甫偉,曾烈光;異步FIFO的VHDL設(shè)計[J];電子技術(shù)應用;2001年06期

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本文編號:2334227

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