【摘要】：近年來,數(shù)字信號處理技術(shù)得到了迅速的發(fā)展。在數(shù)字信號處理領(lǐng)域,傳統(tǒng)的傅里葉變換已經(jīng)發(fā)展得比較成熟。但隨著應(yīng)用信號種類的不斷擴展,傅里葉變換逐漸顯露出其在處理非平穩(wěn)信號時的局限性。為了解決上述缺陷,小波變換、Gabor變換、Wigner分布以及分?jǐn)?shù)階傅里葉變換等新的信號分析理論相繼問世。分?jǐn)?shù)階傅里葉變換作為傅里葉變換的廣義形式,因其能夠很好地表達信號的時頻局部特性而受到眾多研究者的青睞。本文對分?jǐn)?shù)階傅里葉變換的離散算法進行了研究與分析,并以FPGA為硬件平臺對其中的一種算法進行了電路的設(shè)計與實現(xiàn)。本文首先對分?jǐn)?shù)階傅里葉變換的定義和性質(zhì)進行了簡要的概述,然后分析和對比幾種不同的離散算法并闡述了它們各自的優(yōu)缺點,最后選擇了線性組合型的離散算法作為研究對象。此算法繼承了連續(xù)分?jǐn)?shù)階傅里葉變換的大部分性質(zhì),易于工程實現(xiàn)。線性組合型的離散算法有兩種實現(xiàn)方式,即串行方法實現(xiàn)和并行方法實現(xiàn)。本文對比了這兩種實現(xiàn)方式。并行實現(xiàn)方式所需要的物理資源是難以承受的,串行實現(xiàn)方法卻具有規(guī)則的計算結(jié)構(gòu),適合于VLSI實現(xiàn)。因此,本文將以串行實現(xiàn)方式來設(shè)計該離散算法的電路結(jié)構(gòu)。通過對相關(guān)理論的分析,本文給出了線性組合型的離散算法的電路設(shè)計思路。本文提出的電路結(jié)構(gòu)一共分成四個模塊:(1)CORDIC模塊;(2)奇數(shù)點IFFT模塊;(3)矩陣向量乘模塊;(4)邏輯控制模塊。本文在CORDIC模塊中使用Baker預(yù)測降低了電路資源消耗,在奇數(shù)點IFFT模塊中充分利用Winograd算法減少了乘法的次數(shù),在矩陣向量乘模塊中通過數(shù)據(jù)重新排序技術(shù)提高了流水線電路的計算效率。本文設(shè)計的電路擁有三種工作模式,并且可以很容易地擴展到其它的分?jǐn)?shù)階信號變換。該電路結(jié)構(gòu)在FPGA上實現(xiàn)所得的結(jié)果經(jīng)測試精度高,最高工作頻率可達291MHz。
[Abstract]:In recent years, digital signal processing technology has been rapidly developed. In the field of digital signal processing, the traditional Fourier transform has been more mature. However, with the continuous expansion of the types of applied signals, Fourier transform gradually reveals its limitations in the processing of non-stationary signals. In order to solve the above problems, new signal analysis theories such as wavelet transform Gabor transform Wigner distribution and fractional Fourier transform have been developed one after another. As a generalized form of Fourier transform, fractional Fourier transform (FRT) is favored by many researchers for its ability to express the time-frequency local characteristics of signals. In this paper, the discrete algorithm of fractional Fourier transform is studied and analyzed, and one of the algorithms is designed and implemented using FPGA as the hardware platform. In this paper, the definition and properties of fractional Fourier transform are briefly summarized, then several discrete algorithms are analyzed and compared, and their respective advantages and disadvantages are described. Finally, the linear combinatorial discrete algorithm is chosen as the research object. This algorithm inherits most of the properties of continuous fractional Fourier transform and is easy to be implemented in engineering. There are two ways to realize linear combinatorial discrete algorithm: serial method and parallel method. This paper compares these two methods of implementation. The physical resources required for parallel implementation are unbearable, but the serial implementation method has a regular computing structure, which is suitable for VLSI implementation. Therefore, this paper designs the circuit structure of the discrete algorithm by serial implementation. Based on the analysis of relevant theories, the circuit design idea of linear combinatorial discrete algorithm is given in this paper. The proposed circuit structure is divided into four modules: (1) CORDIC module; (2) odd point IFFT module; (3) matrix vector multiplication module; (4) logic control module. In this paper, Baker prediction is used in CORDIC module to reduce circuit resource consumption, and Winograd algorithm is fully used in odd-point IFFT module to reduce the times of multiplication. The efficiency of pipeline circuit is improved by data reordering in matrix vector multiplication module. The circuit designed in this paper has three working modes and can be easily extended to other fractional signal transformations. The result of the circuit structure realized on FPGA has high precision and the highest working frequency can reach 291 MHz.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TN911.72

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本文編號：2154441