面向光纖通道的SerDes電路IP化技術(shù)研究
發(fā)布時間：2018-07-17 04:00
【摘要】：隨著日益增長的高速傳輸?shù)男枰?傳統(tǒng)的并行通信技術(shù)已經(jīng)成為進一步提高數(shù)據(jù)傳輸速率的主要瓶頸,限制了系統(tǒng)整體性能的提升。在這種情況下,以SerDes為代表的串行通信技術(shù)以其較低的功耗、簡單的系統(tǒng)互聯(lián)、更強的抗干擾能力以及更高的傳輸速率等優(yōu)點,正在逐步取代傳統(tǒng)的并行通信技術(shù)而成為當(dāng)前高速通信的主流。SerDes是英文Serializer(串化器)/Deserializer(解串器)的縮寫。在發(fā)送端,用于將低速的并行CMOS數(shù)字信號轉(zhuǎn)換為高速的串行低電壓差分信號并通過光纖或銅線發(fā)送出去;在接收端,再將高速的低電壓差分信號正確的轉(zhuǎn)換為CMOS電平信號后進行串并轉(zhuǎn)換輸出。它是一種時分多用、點對點的串行通信技術(shù),廣泛應(yīng)用于光纖通信、接入設(shè)備、WI系統(tǒng)以及工業(yè)控制系統(tǒng)。這種點對點的串行通信技術(shù)不需要傳輸同步時鐘,所以傳輸速率可以達到很高,而且互連時最少只需要一對傳輸線,可以有效減少系統(tǒng)互連的復(fù)雜度,降低總體成本。一個典型的SerDes芯片包括:8B/10B編解碼器、產(chǎn)生高速時鐘的鎖相環(huán)、LVDS收發(fā)器以及從接收信號中恢復(fù)出時鐘的CDR電路。本文旨在研究SerDes電路的IP化并將其用于光纖通信的物理層接口中。圍繞SerDes電路IP化所要交付的內(nèi)容,做了如下一些工作:第一,詳細研究了IP化流程,IP軟核、固核和硬核的異同以及它們在IP化過程中所要提交的內(nèi)容;第二,詳細研究了SerDes電路的原理圖、版圖以及特殊I/O;第三,采用模擬硬件描述語言Verilog-A對SerDes進行行為建模;第四,采用Synopsys的NanoTime對Ser Des進行時序建模。最后,以0.13μm CMOS工藝實現(xiàn)的一款工作在0.5-1.5Gb/s速率的SerDes芯片為基礎(chǔ),全面測試了其性能。實際測試表明,所建立的模型與實際芯片的測試結(jié)果相吻合。本文的研究成果期冀于為后續(xù)的SerDes芯片以IP的形式集成到光纖通信的物理層接口中提供參考價值以及研究基礎(chǔ)。
[Abstract]:With the increasing demand of high-speed transmission, the traditional parallel communication technology has become the main bottleneck to further improve the data transmission rate, which limits the overall performance of the system. In this case, the serial communication technology represented by SerDes has the advantages of low power consumption, simple system interconnection, stronger anti-interference ability and higher transmission rate, etc. It is gradually replacing the traditional parallel communication technology to become the mainstream of high speed communication. SerDes is the abbreviation of Serializer / Deserializer. At the transmitter, it is used to convert a low-speed parallel CMOS digital signal to a high-speed serial low-voltage differential signal and transmit it through optical fiber or copper wire; at the receiving end, Then the high-speed low-voltage differential signal is converted to CMOS level signal correctly and then serially converted to output. It is a kind of time division multipurpose, point to point serial communication technology, which is widely used in optical fiber communication, access equipment and industrial control system. This kind of point-to-point serial communication technology does not need to transmit synchronous clock, so the transmission rate can reach very high, and only a pair of transmission lines are required for interconnection, which can effectively reduce the complexity of system interconnection and reduce the overall cost. A typical SerDes chip includes a: 8B / 10B codec, a phase-locked loop LVDS transceiver that generates a high speed clock, and a CDR circuit that recovers the clock from the received signal. The purpose of this paper is to study the IP of Serdes circuit and use it in the physical layer interface of optical fiber communication. Some work has been done around the contents of the IP of SerDes circuit. First, the IP soft core, the similarities and differences between the fixed core and the hard core, and the contents to be submitted in the IP process are studied in detail. The schematic diagram, layout and special I / O of SerDes circuit are studied in detail. Thirdly, SerDes is modeled with the analog hardware description language Verilog-A; fourth, the sequential modeling of SerDes is done by using Synopsys NanoTime. Finally, based on a 0.13 渭 m CMOS SerDes chip operating at 0.5-1.5 GB / s rate, the performance of the chip is tested. The actual test results show that the model is in agreement with the actual chip test results. The research results in this paper are expected to provide reference value and research basis for the subsequent SerDes chip to be integrated into the physical layer interface of optical fiber communication in the form of IP.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TN929.11
[Abstract]:With the increasing demand of high-speed transmission, the traditional parallel communication technology has become the main bottleneck to further improve the data transmission rate, which limits the overall performance of the system. In this case, the serial communication technology represented by SerDes has the advantages of low power consumption, simple system interconnection, stronger anti-interference ability and higher transmission rate, etc. It is gradually replacing the traditional parallel communication technology to become the mainstream of high speed communication. SerDes is the abbreviation of Serializer / Deserializer. At the transmitter, it is used to convert a low-speed parallel CMOS digital signal to a high-speed serial low-voltage differential signal and transmit it through optical fiber or copper wire; at the receiving end, Then the high-speed low-voltage differential signal is converted to CMOS level signal correctly and then serially converted to output. It is a kind of time division multipurpose, point to point serial communication technology, which is widely used in optical fiber communication, access equipment and industrial control system. This kind of point-to-point serial communication technology does not need to transmit synchronous clock, so the transmission rate can reach very high, and only a pair of transmission lines are required for interconnection, which can effectively reduce the complexity of system interconnection and reduce the overall cost. A typical SerDes chip includes a: 8B / 10B codec, a phase-locked loop LVDS transceiver that generates a high speed clock, and a CDR circuit that recovers the clock from the received signal. The purpose of this paper is to study the IP of Serdes circuit and use it in the physical layer interface of optical fiber communication. Some work has been done around the contents of the IP of SerDes circuit. First, the IP soft core, the similarities and differences between the fixed core and the hard core, and the contents to be submitted in the IP process are studied in detail. The schematic diagram, layout and special I / O of SerDes circuit are studied in detail. Thirdly, SerDes is modeled with the analog hardware description language Verilog-A; fourth, the sequential modeling of SerDes is done by using Synopsys NanoTime. Finally, based on a 0.13 渭 m CMOS SerDes chip operating at 0.5-1.5 GB / s rate, the performance of the chip is tested. The actual test results show that the model is in agreement with the actual chip test results. The research results in this paper are expected to provide reference value and research basis for the subsequent SerDes chip to be integrated into the physical layer interface of optical fiber communication in the form of IP.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2014
【分類號】：TN929.11
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